Patents Examined by W. Burns
  • Patent number: 5552443
    Abstract: N,N'-disubstituted-amidines, e.g., of the formula ##STR1## wherein R, R' and R" are substituted or unsubstituted hydrocarbon and/or heterocyclic groups.Methods are provided for the treatment or prophylaxis of anxiety in an animal for treating psychosis, and for treating hypertension by administering an effective amount of an N,N'-disubstituted amidine which, preferably, has a high affinity for the sigma receptor.
    Type: Grant
    Filed: January 18, 1994
    Date of Patent: September 3, 1996
    Assignees: Oregon Health Sciences University, The University of Oregon
    Inventors: John F. W. Keana, Eckard Weber
  • Patent number: 5252913
    Abstract: A combined current and voltage measuring sensor for measuring voltage and current on a primary conductor, the sensor including a cast resin body having therein a aluminum support, the support having an aluminum encasement mounted thereto. An air core coil is encapsulate with the encasement within the cast resin body adjacent a grooved portion in the cast resin body for maintaining the primary conductor in the top of the cast resin body. The groove and the aluminum encasement cooperate to precisely locate the primary conductor with respect to the air core coil. A keeper assembly mechanically maintains and locates the primary conductor in the groove and further provides an electrical connection from the primary conductor to the voltage measuring apparatus of the sensor. A corona shield encapsulated within the cast resin body is at the same potential as the conductor and is interposed between the air coil and the groove of the cast resin body.
    Type: Grant
    Filed: April 28, 1989
    Date of Patent: October 12, 1993
    Assignee: Square D Company
    Inventors: Paul P. Falkowski, Peter H. Forest, Donald W. Selby
  • Patent number: 4995039
    Abstract: In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.
    Type: Grant
    Filed: September 22, 1988
    Date of Patent: February 19, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Sakashita, Ichiro Tomioka, Takeshi Hashizume
  • Patent number: 4983910
    Abstract: A millimeter-wave active probe for use in injecting signals with frequencies above 50GHz to millimeter-wave and ultrafast devices and integrated circuits including a substrate upon which a frequency multiplier consisting of filter sections and impedance matching sections are fabricated in uniplanar transmission line format. A coaxial input and uniplanar 50 ohm transmission line couple an approximately 20 GHz input signal to a low pass filter which rolls off at approximately 25 GHz. An input impedance matching section couples the energy from the low pass filter to a pair of matched, antiparallel beam lead diodes. These diodes generate odd-numberd harmonics which are coupled out of the diodes by an output impedance matching network and bandpass filter which suppresses the fundamental and third harmonics and selects the fifth harmonic for presentation at an output.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: January 8, 1991
    Assignee: Stanford University
    Inventors: Gholamreza Majidi-Ahy, David M. Bloom
  • Patent number: 4980635
    Abstract: A carrier for an integrated circuit package is disclosed which comprises a base (30) suitable for receiving an integrated circuit package with unformed leads (20') or formed leads (20), a cover (60), flexible material (66), such as an elastomer, disposed between the cover (60) and base (30) surfaces, and pressure is maintained across the cover (60) and base (30) by way of finger (44) on a clip (40) on the base (30) engaging latching edges (68) of cover (60). The leads (22) of the integrated circuit package (20, 20') are thereby secured in position by the elastomeric material (66) which forms itself partially around each of the leads in response to pressure applied across the base (30) and cover (60) as hereinabove described. The disclosed invention eliminates the need for separate grooves or nests in the base (30) of the carrier for each lead of the integrated circuit package.
    Type: Grant
    Filed: December 26, 1984
    Date of Patent: December 25, 1990
    Assignee: Hughes Aircraft Company
    Inventors: R. Thomas Walton, James A. Hathaway, Michael D. Runyan, Michael L. Turnage
  • Patent number: 4972414
    Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing an oscillator input signal to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) are providing in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: November 20, 1990
    Assignee: International Business Machines Corporation
    Inventors: John M. Borkenhagen, Steven M. Douskey, Jerome M. Meyer
  • Patent number: 4970461
    Abstract: A circuit is tested for unwanted shorts and opens by positioning the circuit between a pair of electrodes in a chamber filled with an inert gas with the circuit conductors facing one of the electrodes. The circuit is charged by applying a selected voltage to the electrodes to produce an electric field extending generally perpendicular to the circuit, the voltage polarity being such that the one electrode carries the negative electrical charge. The circuit is then subjected to a pulsed laser beam brought to a focus between the one electrode and a selected spot on a conductor of the circuit so as to ionize the chamber gas at the beam focus to form a plasma so that an electric charge is imparted to that spot and to other circuit conductor portions having electrical continuity with that spot.
    Type: Grant
    Filed: June 26, 1989
    Date of Patent: November 13, 1990
    Inventor: Andrew J. LePage
  • Patent number: 4967152
    Abstract: An apparatus which is used for non-contact electrical measurement and physical alteration of certain characteristics and properties of electronic conductor devices. The apparatus includes a focused source of ultraviolet light which is capable of micron and sub-micron resolution.In the measurement mode the apparatus measures the energy of electrons ejected from a measurement site by the UV beam. This measurement is accomplished at a nulling/repelling device. In the alteration mode, the focused UV light beam interacts with various compounds, for example chemical gases, to create a selective reaction at specific locations at the surface of the device being operated upon.The measurement function can be related to voltage, current, temperature or the like and may be either qualitative or quantitative while being made in a non-contact basis.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: October 30, 1990
    Assignee: Ultra-Probe
    Inventor: Joseph M. Patterson
  • Patent number: 4967151
    Abstract: A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors.
    Type: Grant
    Filed: October 11, 1989
    Date of Patent: October 30, 1990
    Assignee: International Business Machines Corporation
    Inventors: Arnold E. Barish, David A. Kiesling, Mark D. Mayo, Walter A. Svarczkopf
  • Patent number: 4967150
    Abstract: In the method and apparatus for the phase measurement of arbitrary signals at a measuring point, for example, of surface waves on piezoelectrical substrates, the surface waves are excited on the surface of a specimen having piezoelectrical features. The measuring point on the specimen surface is scanned by a particle beam and a secondary electrical signal at the measuring point is supplied to an evaluation circuit via a detector. A phase detector within the evaluation circuit is operated in a linear region of its output characteristic curve with the use of a feedback. This makes it possible to keep the phase at the phase detector constant. The phase of the signal to be examined, for example, of the surface wave, which is produced at a interdigital transducer is influenced due to the feedback.
    Type: Grant
    Filed: September 16, 1988
    Date of Patent: October 30, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans D. Brust
  • Patent number: 4965513
    Abstract: A motor current noise signature analysis method and apparatus for remotely monitoring the operating characteristics of an electric motor-operated device such as a motor-operated valve. Frequency domain signal analysis techniques are applied to a conditioned motor current signal to distinctly identify various operating parameters of the motor driven device from the motor current signature. The signature may be recorded and compared with subsequent signatures to detect operating abnormalities and degradation of the device. This diagnostic method does not require special equipment to be installed on the motor-operated device, and the current sensing may be performed at remote control locations, e.g., where the motor-operated devices are used in accessible or hostile environments.
    Type: Grant
    Filed: November 14, 1989
    Date of Patent: October 23, 1990
    Assignee: Martin Marietta Energy Systems, Inc.
    Inventors: Howard D. Haynes, David M. Eissenberg
  • Patent number: 4963824
    Abstract: A method and circuitry for testing in situ the components mounted on a circuit board. First, a component is removed from the board. A testing circuit is then installed in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.
    Type: Grant
    Filed: November 4, 1988
    Date of Patent: October 16, 1990
    Assignee: International Business Machines Corporation
    Inventors: Edward P. Hsieh, Maurice T. McMahon, Henri D. Schnurmann
  • Patent number: 4962356
    Abstract: Improved performance and reliability is obtained in test sockets for integrated circuits (ICs). Sufficient over-travel is provided to prevent pinching when the IC and its carrier are inserted in the test socket and the lid is latched closed. A power operated piston applies controllable and uniform pressure to force the IC leads onto contact pins in the test socket base. This controllable and uniform pressure prevents gouged IC leads, bent test socket pins, and other damage that prevents proper electrical and mechanical contact between IC leads and contact pins resulting in erroneous indications of faulty IC operation.
    Type: Grant
    Filed: August 19, 1988
    Date of Patent: October 9, 1990
    Assignee: Cray Research, Inc.
    Inventors: Delvin D. Eberlein, Peter Wehner
  • Patent number: 4952871
    Abstract: A printed circuit board having thereon a plurality of conductors including onnection points is tested for insulation resistance between the conductors by measuring current flowing between one conductor and the other conductors in an arrangement whereby each connection point is connectable to a first potential through a first transistor and to a second potential through a second transistor and a current measuring device. During testing, only a single connection point of each conductor is connected to the second potential, and all other transistors of that conductor are mechanically isolated from electrical connection with respective connection points. This prevents leakage current through the transistors associated with the other connection points of a given conductor.
    Type: Grant
    Filed: January 24, 1990
    Date of Patent: August 28, 1990
    Assignee: Mania Elektronik Automatisation Entwicklung und Geratebau GmbH
    Inventors: Hubert Driller, Paul Mang
  • Patent number: 4952872
    Abstract: A circuit board testing apparatus includes a plurality of contact elements located in a contact array plane. The contact elements are connected to an electronic control and test structure and during testing are connected through longitudinally rigid test pins to contact portions of a connection carrier or circuit board to be tested. The contact elements are mounted to yield resiliently and are supported against the contact pressure applied during testing. The contact elements are in the form of electrically conductive compression springs located and guided directly in bores in a spring array body formed of an electrically insulating material. The rigid test pins seat directly on the compression springs.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: August 28, 1990
    Assignee: Mania Elektronik Automatisation Entwicklung und Geratebau GmbH
    Inventors: Hubert Driller, Paul Mang
  • Patent number: 4950980
    Abstract: A socket having an array of terminals adapted for insertion into a burn-in board is adapted to interconnect respective pins of a high pin density integrated circuit package to the terminals. The socket includes a lid with an array of holes for receiving the pins and registering the pins with underlying terminal openings and a cam mechanism actuable to move the lid relative to the terminals to cause the pins to make contact with the terminals within the openings. Mounting of the package on the socket and insertion of the pins into underlying terminal openings is accomplished with zero insertion force applied to the pins. Actuation of the cam mechanism causes the pins to contact respective terminals without deforming the pins.
    Type: Grant
    Filed: July 29, 1988
    Date of Patent: August 21, 1990
    Inventor: Wayne K. Pfaff
  • Patent number: 4949031
    Abstract: Apparatus for environmental stress screening of electronic components includes a chamber having a wall defining an opening therein. A product carrier pallet has a portion dimensioned and configured to inserted in the opening. The portion of the product carrier pallet has a periphery and structure is provided to seal the periphery with respect to the opening. Structure is provided for conducting a plurality of electrical signals through the portion and for electrical coupling to the structure for conducting. The structure for electrical coupling is disposed outside of the product carrier pallet. The apparatus may include a zero insertion force connector. Other forms of the invention relate to a chamber having opposed aligned openings.
    Type: Grant
    Filed: April 5, 1988
    Date of Patent: August 14, 1990
    Assignee: General Signal Corporation
    Inventors: Norbert I. Szasz, Russell G. Shaw
  • Patent number: 4940931
    Abstract: A timing signal generating circuit generates a timing signal for each sweep timing period. An address generating circuit generates an address corresponding to each sweep timing period and to the magnitude of the input signal, each time it receives the timing signal. An image memory stores data in the address generated by the address generating circuit. A computing unit performs, upon each receipt of the timing signal, a predetermined computation on that data stored in the image memory and generates a result of computation. The computation result represents the frequency of the same address generated for each sweep timing period. A display unit displays the input signal with a luminance level corresponding to the computation result.
    Type: Grant
    Filed: June 20, 1989
    Date of Patent: July 10, 1990
    Assignee: Anritsu Corporation
    Inventors: Aiichi Katayama, Kenichi Kon
  • Patent number: 4939447
    Abstract: A fiber-optic voltage sensor comprises at least one fiber-optic, piezoelectric sensor element (2a, 2b, 2c, 2d), which measures a predeterminable directional component of a local electric field. One or more than one piezoelectric sensor elements (2a, 2b, 2c, 2d) are arranged serially between two ends of the fiber-optic voltage sensor, each piezoelectric sensor element (2a, 2b, 2c, 2d) respectively measuring a directional component of a local electric field, which component lies parallel to a path element assigned to it, the path elements as a whole forming an open polygon connecting the two ends of the fiber-optic voltage sensor. Each sensor element (2a, 2b, 2c, 2d) has a gain which is proportional to a length of the path element assigned to it. In a preferred embodiment, the piezoelectric sensor elements (2a, 2b, 2c, 2d) are connected by spacers (3a, 3b, 3c).
    Type: Grant
    Filed: November 10, 1988
    Date of Patent: July 3, 1990
    Assignee: BBC Brown Boveri AG
    Inventors: Klaus Bohnert, Rolf Kirchhofer
  • Patent number: 4939469
    Abstract: A method for evaluating characteristics of a printed wiring board by measuring the alternating current impedance spectra of the printed wiring board conductor pattern. The method is useful in evaluating a number of different characteristics, such as moisture content, delamination, interlayer thickness and surface characteristics.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: July 3, 1990
    Assignee: Hughes Aircraft Company
    Inventors: Frank A. Ludwig, John McHardy