Abstract: A magnetic disk drive unit using a data surface servo system includes: at least one magnetic disk having a data surface, wherein a region in which servo information including a servo address for use in positioning a head is written and a succeeding data region are arranged alternately on each of a plurality of tracks sectored radially; a magnetic head used for recording or reproducing data and positioned facing the data surface; a modulating/demodulating unit for modulating a write data to thereby supply the modulated data as a record signal to a magnetic head, and for demodulating a signal reproduced by the magnetic head to thereby output the demodulated signal as read data to the magnetic head; and a read/write control unit for controlling a read/write processing of data for the magnetic disk using the magnetic head and the modulating/demodulating unit.

Abstract: During recording of an MPEG information signal on a record carrier (40), transport packets (P.sub.k) are stored in signal blocks in a track (1) on the record carrier (40). x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, where x and y are integers, x.gtoreq.1 and y>1, more specifically, y>x. Further, third block sections (TB) are present in one or more of the second block sections in the y signal blocks of a group for storing additional information, which additional information relates to the specific application of recording and reproducing the MPEG information signal on/from the record carrier.

Abstract: A playback clock signal generating circuit has first and second phase-locked loops PLLs. The first PLL has a voltage-controlled oscillator VCO controllable by an output signal from a low-pass filter for outputting a signal, a variable frequency divider for varying a frequency-dividing number depending on head position information and frequency-dividing the signal from the VCO with the varied frequency-dividing number, a reference oscillator for outputting a reference signal having a frequency equal to a predetermined frequency step, a phase comparator for detecting the phase or frequency difference between an output signal from the variable frequency divider and the reference signal, and outputting the detected phase or frequency difference to the low-pass filter.

Abstract: When modulating by an interleaved NRZI technique by inserting one bit per every m bits of input data series, the frequency characteristics of bit rows varying by the polarity ("0" or "1") of the bit to be inserted are compared and the bit row closer to the desired frequency characteristic is selected as the output series, so that recording is effected by controlling the frequency characteristics of the digital signal.

Abstract: In a disk drive actuator head stack assembly, magnetic transducers including magnetoresistive (MR) read heads are connected to a current source and configured to provide an MR sensor current to each MR head wherein the direction of current flow for the MR sensor current in each MR head is the same relative to the actuator for all of the MR heads in the actuator head stack. This configuration allows all of the MR heads in the head stack assembly to be initialized simultaneously by applying a homogeneous magnetic field to the head stack assembly, thus providing the capability of initializing the MR heads at the actuator or disk drive level rather than requiring that the MR heads be initialized individually.

Abstract: A direct file access system for a magnetic tape where all data files begin at a designated location on the tape. The direct file access system may be used with a reduced rewind data configuration to decrease data access time. The reduced rewind data configuration divides data files into generally equal portions so that data files begin and end at the designated location on the tape, eliminating rewind sequences. A method and system for reducing the number of tape retensioning passes is included to further decrease access time.

Abstract: This method provides new data storage capabilities that are implemented within the industry standard formats of mountable media data recording devices. The new data storage structures are written into regions presently marked on the mountable media as "contents of this region are not of interest" or marked as "no data was recorded within this region". These data storage structures are transparent to present data recording devices and do not disrupt their data processing functions. However, the data storage structures are available to new data recording devices so that new data embedded therein is used to enhance the functionality of the system which utilizes these data storage structures. The types of embedded data may include ECC (error correction codes), tape position information, audit information, security information, mount history, media defect history, authentication notation, generation-identification notation, etc.

Abstract: A write drive logic circuit is described. The write driver logic circuit comprises a set of write drivers, with each one of the set of write drivers having an input and an output, such that each write driver is responsive to an input signal applied to the input to provide a write output signal at the output as a function of the input signal. A set of memory devices (e.g. shift registers) is provided, one for each write driver. Each one of the shift registers stores unique head identification information and includes an output to controllably output a signal representative of the unique head identification information. Furthermore, each one of a set of multiplexers includes an output, a first input coupled to a corresponding one of the outputs of the set of shift registers to receive the signal representative of the unique identification information stored in the respective shift register and a second input coupled to a common write data line that transmits a signal representative of preselected information.

Abstract: A magnetic recording apparatus comprises: a magnetic recording medium for recording a binary signal; a magnetic head for detecting the binary signal; an amplifier for amplifying the binary signal detected by the magnetic head; a channel for outputting the amplifier binary signal in the form of a timing value sequence, the timing value sequence alternately providing positive and negative peak values following the rule of the binary signal a recorded in the recording medium; a temporary judging unit for judging a presently input timing value of the timing value sequence supplied from the channel as one of the positive peak value, the negative peak value, and an intermediate value, in accordance with the relationship with a preceding timing value temporarily judged as one of the positive and negative peak values; a final judging unit for finally setting the preceding timing value as one of the positive and negative peak values and the intermediate value, in accordance with the relationship with the presently inp

Abstract: An apparatus processes an analog audio signal having been stored in a recording medium in a recording order and being reproduced therefrom in a reverse order of the recording order and at a speed .alpha. (.alpha..gtoreq.1) times higher than a recording speed to the recording medium. The analog signal is converted to digital audio signals and written in a memory having head and final addresses. The digital audio signals read from the memory are converted to an output analog audio signal. A controller controlling writing and reading the digital audio signals to and from the memory has a read address controller for controlling read addresses of the memory such that the read addresses repeatedly reciprocate between the head and final addresses. The controller controls the writing such that, if .alpha.>1, the writing starts in sequence from the head or final address when the read address reaches in the vicinity of an address which advances by (.alpha.-1) / .alpha.

Abstract: An audio signal recording and reproducing apparatus can perform realtime processing with a structure having a low cost. The audio signal recording and reproducing apparatus records a series of input audio signals as digital audio data, and reproduces and outputs the input signals using the recorded digital audio data as output audio signals. An input audio signal processing unit converts the series of input audio signals into digital audio data. A data file recording unit records the digital audio data, as digital audio data file information, on a recording medium, the recording medium having a plurality of clusters in which data having a predetermined number of bytes is recorded, the digital audio file information being recorded over a plurality of clusters. A file management information recording unit records on the recording medium file management information representing the reproducing order of the clusters in which the digital audio data file information is recorded.

Abstract: An apparatus for detecting off-track positioning of a disk read/write head seeking a selected data track on a disk having data tracks with embedded servo burst patterns recorded thereon. The apparatus comprises a compare and select component, a charge redistribution A/D converter circuit and an off-track controller. The compare and select component compares and selects from among voltage values corresponding to the servo bursts a pair best representing track centerline as a first servo signal and a second servo signal and determines which of the servo signals is greater. The charge redistribution analog-to-digital (A/D) converter circuit determines if the normalized track position exceeds a position threshold representing a percentage of the normalized track position distinguishing on-track from off-track position through the use of an internal binary-weighted, switched capacitor array DAC and a comparator.

Abstract: A real time defect scanning system integrated into a sampled amplitude read channel for detecting defects in a magnetic storage medium using a discrete time filter having an impulse response substantially matched to an error signature in a read back signal caused by a defect in the medium. The scanning system operates by writing a predetermined bit sequence to the storage device and detecting medium defects upon read back. In a sinusoidal read signal mode, a discrete time notch filter removes the fundamental frequency so that any remaining sidebands indicate a media defect. The discrete time defect filter enhances the signal so that a defect can be detected with a discrete time energy detector. The impulse responses of the notch filter and defect detection filter are programmable in order to adapt the defect scanning system to a particular disk drive, data density, or magnetic media.

Abstract: A disk drive having embedded servo information accesses data without using sector identifier recorded in each sector. When a signal sector pulse signal (SP) at the end of a servo area is detected in a dead state during start up, a first data state for the start of a sector transits to a second data state for the litter region of the sector being divided in accordance with the capacity stored in a current sector's pointer register. At the beginning of the sector, the contents of a next sector's pointer register is stored in current sector's pointer register and the contents of a next sector's operation register is stored in a current sector's operation register. Upon completion of sector processing, the first data state is maintained when the next sector is contiguous. When a terminate instruction is stored in current sector's operation register, the process moves to dead state. When the servo area arrives, the process moves to idle state.

Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

Abstract: A data recording method and apparatus with reduced probability of error occurrence in main data. For recording data on azimuth tracks on a magnetic tape by a rotary magnetic head, each azimuth track is divided into a main data area and margin areas on both sides of the main data area. The main data recorded in the main data area of each track is arrayed two-dimensionally. An error correction code C2 is appended to a data string arrayed in the track direction, while an error correction code C1 is appended to a data string arrayed along the track width. The error correction code C2 is divided into two portions which are arrayed on both sides of the main data area of each track. This reduces the probability of error occurrence in the main data.

Abstract: An arrangement for reading out an information signal from a magnetic record carrier. The arrangement includes a read head having a magneto-resistive element with a first terminal connected to a first point of constant potential, and a second terminal; a bias-current generator having an output for supplying a bias-current to the MR element and an amplifier circuit having a first terminal coupled to the output of the bias-current generator, and a second terminal coupled to the second terminal of the MR so as to form a series arrangement of the bias-current generator, the amplifier circuit and the MR element. At an output terminal of the amplifier circuit, the information signal is available.

Abstract: An input video signal composed of a luminance signal Y, and color difference signals PR and PB. The video signal is converted into digital signals. A plurality of coding paths are provided. The digital video signals are processed in shuffling circuit, DCT circuit, quantizing circuit, variable length code encoding circuit, and frame segmenting circuit on the coding paths. The signals encoded on the coding paths are converted into data with two channels. The data with two channels are recorded on a recording medium. The data are allocated to a predetermined region of a magnetic tape so that a block of data is reproduced as bursts on a screen in a variable speed reproduction mode.

Abstract: A multipath channel apparatus for a data storage device wherein data is stored on a storage medium and is read from the storage medium by a transducer or for a data communications system wherein data is transmitted to a receiver. A data channel having a plurality of data paths is operatively connected to the transducer to receive data read from the storage medium by the transducer, or operatively connected to receive data demodulated by the receiver or base band data received by the receiver. Preferably, each of the data paths has a differing parameter value. An error checking unit checks customer and redundancy data from each of the data paths. A selecting unit, which is responsive to the error checking unit, selects data from one of the data paths. In a preferred embodiment, the data stored on a storage medium includes a data field and an error correcting code field, and the customer and redundancy data from each of the data paths is checked using a calculated error correcting code sydrome.

Abstract: A "zero phase start" optimization circuit for a Partial Response, Maximum Likelihood ("PRML") data channel dynamically determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer, a summing junction, either an absolute value or squaring function, and an integrator. A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.