Abstract: During an initialization of a simulation of the behavior of an industrial plant containing a number of components, a particularly reliable parameter input is intended to be ensured with a particularly low outlay. To this end, in an initialization method provision is made, according to the invention, that for each component a component type is identified in each case and, in circuit terms, is characterized by a number of inputs and by a number of outputs for one parameter in each case. The initialization method uses a stored component-type-specific signal flow structure for the parameter of each output for specifying whether a parameter input is requested for a component.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by moving selected software components of the system to a hardware implementation. In one aspect, the tool automatically generates a performance profile of an original form of the system. The performance profile of the original form of the system may be used to select software components of the system to be moved to hardware. In another aspect, the tool generates an estimated performance profile of a repartitioned form of the system by modifying the performance profile of the system. The estimated performance profile of the repartitioned system is compared to the performance profile of the original form of the system to verify benefits, if any, of repartitioning. Such verification is accomplished without the need to actually repartitioning the system or measuring the performance of the entire repartitioned system.

Abstract: An implementation framework, including methodologies and the architecture, for a real-time traffic emulation for packet switched networks. The framework uses extended finite state machines to model the traffic flows that are to be emulated. A simple yet flexible FMS-based scripting language is proposed to describe these flows. An event-driven approach to schedule CPU among flows is also adopted.

Abstract: A simulator of intelligent workstations at level 2 the OSI model for generating complete LAN frames for testing a system under test. The simulator includes a scripting facility that represents the actions of the human end-user at the client workstation. By providing a scripting facility, different complexions of a workload can be impressed upon the system under test without the need for human end-users nor the need for rebuilding the simulation tool. The simulator includes embedded protocol stacks allowing manipulation of the simulated LAN frames. The simulator also includes one or more embedded protocol application modules for emulating actions of an application, e.g., web browser, and enabling the handling of dynamic, application-related events.

Abstract: Process for designing flight controllers, in which first for the rigid airplane and then for the elastic airplane the damping and the phase delay for each excitation frequency is determined, and the flight controller is adapted in such a manner that the structural responses to each excitation frequency for both the rigid airplane and the elastic airplane in the open control circuit outside two design fields, applicable to the elastic airplane, are laid around the instability points in the data field comprising damping and phase delay, whereby for the design of the elastic airplane between the phase delays of −270 degrees and −495 degrees, a damping exceeding −6 dB is allowed.

Abstract: A solid freeform fabrication method and apparatus for making objects in a layer by layer manner in which the objects have special geometrical features requiring specialized control parameters. The method and apparatus automatically determines and selects the build parameters for the build process based on automatic part feature recognition. A general build style is first determined having a plurality of default parameters for building the object. Data representing the object is imported and oriented with a Z-axis. The data is then processed by slicing software that automatically identifies special build types for specific ranges of Z-values and selects the alternative parameters needed to successfully build these features. Preferably a look-up table contains special sets of values for the parameters for each special build type possible in which the slicing algorithm can select from. During slicing, operator intervention is not needed to prepare all the parameters necessary for a successful build.

Abstract: A hardware abstraction layer operates as a system architectural layer between a real-time operating system and an underlying configurable processor. The hardware abstraction layer provides an abstraction of processor-specific functionality to the operating system. In particular, it abstracts configurable processor features visible to the operating system to provide a uniform, standardized interface between the operating system and the configurable processor on which it runs. Thus, an operating system running on top of the hardware abstraction layer will work on all configurations of the processor which differ from one another only in the configuration parameters covered by the hardware abstraction layer. The hardware abstraction layer may be generated using the same information that is used to describe the features being configured in the configurable processor.

Abstract: A method for generating a model of a portion of the floor of a body of water from a plurality of depth measurement sources includes determining an overlap of any of the plurality of depth measurement sources with another depth measurement source and generating a relative shift between any two depth measurement sources that overlap. For each depth measurement source that overlaps with at least one other source, generating an overall shift based on the generated relative shifts. The method also includes generating a desired grid having a plurality of grid nodes and generating a model depth at a plurality of the grid nodes based, at least in part, on a global shift for the measurements of the plurality of sources based on the relative shift. Further, an output is generated of all model depths at respective grid nodes.

Abstract: In testing a system, coverage of the testing is obtained by maintaining a store of information that is populated as the testing progresses. The store maintains information about the ranges of system variables that are employed during the testing. At the conclusion of the testing, the coverage of the testing is reported out, to permit the designer to assess whether other queries ought to be formulated, or whether portions of the system are superfluous. The testing can employ simulations, formal verifications, or some other techniques.

Abstract: A model seismic image of a subsurface seismic reflector is constructed, wherein a set of source and receiver pairs is located, and a subsurface velocity function is determined. Specular reflection points are determined on the subsurface seismic reflector for each of the source and receiver pairs. A Fresnel zone is determined on the subsurface seismic reflector for each of the specular reflection points, using the subsurface velocity function. One or more seismic wavelets are selected and a set of image points is defined containing the subsurface seismic reflector. A synthetic seismic amplitude is determined for each of the image points by summing the Fresnel zone synthetic seismic amplitude for all of the Fresnel zones that contain the image point, using the seismic wavelets. The model seismic image of the subsurface seismic reflector is constructed, using the synthetic seismic amplitudes at the image points.

Abstract: The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present invention, a host processor is programmed in its native source and machine code language, and an emulated second processor is programmed in a different native source or machine code language particular to that emulated processor, to allow programming specialists in the different processors to develop common code for use on the same host processor. A multitasking operating system is included to allow time sharing operation between instructions from program code relating to the host processor (e.g., a DSP in the disclosed embodiment), and different program code relating to the emulated processor. The program code relating to the host processor (e.g., DSP) is written in program code which is native to the DSP, while the program code relating to the emulated processor (e.g.

Abstract: A processing system employs a plurality of processing apparatuses in which a shared operation can be executed. To this end, first a type of the shared operation is designated, and then a target user of one of the processing apparatuses for a shared operation in executing the designated shared operation is designated, the target user being either a target user individual or a target user group. Finally, execution of an inquiry process is controlled in accordance with a combination of the designated type of shared operation and the designated target user.

Abstract: Provided are test systems, methods, and media which allow a user to script any type of test or model scenario based on a particular type of network traffic (e.g., protocol interaction). In preferred embodiments, the script provides for the generation of packets (stimuli) which are used to provoke responses in order to model or test proper operation of one or more network protocols. The invention includes a scripting language, also referred to as a stimulus/response engine, which includes commands specifying a state change of a network device, and provides for the establishment of packet filters based on expected network traffic, receiving and matching arriving packets with packet filters, and, where there is a match, conducting actions specified by the user in the script. A stimulus/response engine (SRE) in accordance with the present invention is dynamic it that it accommodates patterns (packet filters) which are modified during test runs.

Abstract: A network address supply system includes terminal equipments, a server, and a switching HUB to which the terminal equipments and the server are connected via communication lines. Each terminal equipment includes an address supply requesting unit. The switching HUB includes interfaces, a first line data storing unit, and a communication line control unit that when one of the interfaces receives an address supply request broadcast packet from one of the terminal equipments, transmits the address supply request broadcast packet to only an interface corresponding to the interface information stored in the first line data storing unit. The server includes a network address storing unit and an address supplying unit that when receiving the address supply request broadcast packet, broadcasts an address broadcast packet containing an unused network address stored in the network address storing unit as a response packet to the address supply request broadcast packet.

Abstract: Modems are implemented using a language made of instructions or commands which are based on the types of signals needed to be generated or processed by the modem. That is, the commands are individually tailored to specify the signals to be sent or processed. The modems can be implemented on a digital signal processor or on a host. The language permits a terseness of expression resulting in smaller code, makes it easy to express the needed manipulations required for modem functionality and permits faster execution.

Abstract: A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.

Abstract: According to a broad aspect of a preferred embodiment of the invention, a Customer Quality of Service Management system is provided. First, a hybrid network event is received which may include customer inquiries, required reports, completion notification, quality of service terms, service level agreement terms, service problem data, quality data, network performance data, and/or network configuration data. Next, the system determines customer reports to be generated and generates the customer reports accordingly based on the event received.

Abstract: The inventive mechanism compares system states resulting from emulation of the same block of source code by different emulation technologies within a dynamic compiler. A set of initial conditions, parameters of the system state S1, preceding any emulation is stored for later use. Then, the block of source code is emulated by an interpreter generating a system state S2, the parameters of which are contained partly in the system registers and partly in memory locations accessed by the interpreter. The status of the memory locations representing system state S2 are stored in a Write History Stack, while the register values representing system state S2 are saved to a reserved portion of memory. Next, the initial conditions, represented by the parameters of the system state S1, are restored to the appropriate registers and memory location values affected by the interpreter. Then, the same block of code is emulated employing dynamic translation leading to a third system state S3.

Abstract: A process for synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a cell separation process assigns (x,y) locations to each of the cells based on the weights. The wires are then examined to determine their respective performance characteristics. The wires are iteratively re-weighted, and the cells moved according to the new weightings. Next, the cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of each of the gates can be either scaled up or down accordingly. Again, the nets are iteratively examined and their weights are adjusted appropriately. The cells are spaced apart according to the new weights.