Abstract: In an IC chip having an interlevel insulation film constituted by a first level silicon oxide film, a spin-on-glass film, a second level silicon oxide film, the SOG film is partially removed in a buffer region of a closed loop shape inside of the chip periphery and surrounding the chip inner region. The second level silicon oxide film and a passivation insulation film are formed covering the SOG film and buffer region. Water contents are intercepted by the buffer region and will not reach the element region. It is therefore possible to prevent an inversion of the conductivity type at the surface of a well region in the element region or a corrosion of wiring layers, thereby improving the reliability of an IC device.

Abstract: A circuit in accordance with the invention has a complementary pair of a MISFET and a COMFET with their drains connected together. This allows fabrication on a single substrate for greater reliability and reduced cost. The circuit can be used in a full or one half "H-bridge" configuration for controlling current through a load such as a motor.