Abstract: Provided is a device in which each pixel of an imaging element is divided into a plurality of pixel regions with different sensitivities of which central positions coincide with each other, and a high dynamic range image is generated on the basis of an output of each region. An imaging element is included on which imaging light is incident through a micro lens corresponding to each pixel. Each pixel of the imaging element includes a high-sensitive pixel region at a central portion of the pixel and a low-sensitive pixel region configured at an inner peripheral portion near sides of the pixel and surrounding the high-sensitive pixel region, and has a configuration in which central positions of the high-sensitive pixel region and the low-sensitive pixel region coincide with each other. Moreover, a medium-sensitive pixel region may be included between the high-sensitive pixel region and the low-sensitive pixel region.

Abstract: A display device that has a function of emitting visible light and infrared light and a function of detecting light. The display device is a display device including a first light-emitting device, a second light-emitting device, and a light-receiving device, in a display portion. The first light-emitting device includes a first pixel electrode, a first optical adjustment layer, a first light-emitting layer, a second light-emitting layer, and a common electrode. The second light-emitting device includes a second pixel electrode, a second optical adjustment layer, the first light-emitting layer, the second light-emitting layer, and the common electrode. The light-receiving device includes a third pixel electrode, an active layer, and the common electrode. The active layer includes an organic compound. The first light-emitting device emits infrared light emitted by the first light-emitting layer. The second light-emitting device emits visible light emitted by the second light-emitting layer.

Abstract: A multiple-gate transistor comprises a source, a drain spaced apart from the source, a semiconductor region disposed between the source and drain, and an insulating region disposed over the semiconductor region. A current control gate controls a magnitude of current flowing between the source and drain through the semiconductor region in dependence on a first electric field applied to the current control gate, and is separated from the source by the semiconductor region and the insulating region. A switching gate permits current to flow between the source and drain through the semiconductor region in dependence on a second electric field applied to the switching gate. The transistor's conduction state can be controlled by varying the second electric field applied to the switching gate, whilst varying the first electric field that is applied to the current control gate can set the magnitude of the current through the multiple-gate transistor.

Abstract: A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer.

Abstract: A package structure including a first radio frequency die, a second radio frequency die, an insulating encapsulant, a redistribution circuit structure, a first oscillation cavity and a second oscillation cavity is provided. A first frequency range of the first radio frequency die is different from a second frequency range of the second radio frequency die. The insulating encapsulant laterally encapsulates the first radio frequency die and the second radio frequency die. The redistribution circuit structure is disposed on the first radio frequency die, the second die and the insulating encapsulant. The first oscillation cavity is electrically connected to the first radio frequency die, and the second oscillation cavity is electrically connected to the second radio frequency die.

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

Abstract: In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective voltage supply line, connected to a first capacitor electrode and a semiconductor material layer. An orthographic projection of a first anode on a base substrate at least partially overlaps with an orthographic projection of a node connecting line in a respective first subpixel. An orthographic projection of a second anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective second subpixel. An orthographic projection of a third anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective third subpixel. An orthographic projection of a fourth anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective fourth subpixel.

Abstract: A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a base substrate, a first insulation layer, a first electrode pattern, a connecting electrode pattern, a second electrode, a light-emitting functional layer, and a first filling layer. The second electrode is connected with the connecting electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other. The light-emitting functional layer is located between the first electrode pattern and the second electrode. The first filling layer is located between the connecting electrode pattern and the first electrode pattern. The first filling layer and the light-emitting functional layer are different layers; a portion of the first insulation layer that is located between the first electrode pattern and the connecting electrode pattern has a groove, and the first filling layer is at least partially located in the groove.

Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a pixel definition layer, an organic light-emitting layer, a cathode layer, an encapsulation layer, and an absorption layer. The absorption layer is arranged on one side of the pixel definition layer away from the array substrate. The absorption layer is arranged corresponding to at least a portion of the pixel definition layer in a curved display region for selectively absorbing at least one color light, so as to reduce a risk of color shift in a white screen at large viewing angles without causing color shift of images at a vertical viewing angle.

Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.

Abstract: An OLED display panel comprises an array substrate and metal wiring layers, wherein one part of metal lines is arranged in a direction perpendicular to a first dam, and the other part of the metal lines forms acute angles with the first dam. A plurality of first grooves are defined in a fan-out area and arranged along the metal lines, and a plurality of second grooves are defined in the array substrate corresponding to a part of an area and arranged in the direction perpendicular to the first dam.

Abstract: A semiconductor substrate structure including a first group of circuit structure and a second group of circuit structure is provided. The first group of circuit structure includes multiple first wiring layers and multiple first conductive connectors, and each of the first conductive connectors includes a conductive cap. The second group of circuit structure includes multiple second wiring layers and multiple second conductive connectors. The first group of circuit structure and the second group of circuit structure are electrically connected through bonding of the first conductive connectors and the second conductive connectors to form a multilayer redistribution structure. A manufacturing method of the semiconductor substrate structure is also provided.

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.

Abstract: The present technique relates to a solid-state imaging device and an imaging apparatus that enable provision of a solid-state imaging device having superior color separation and high sensitivity. The solid-state imaging device includes a semiconductor layer in which a surface side becomes a circuit formation surface, photoelectric conversion units PD1 and PD2 of two layers or more that are stacked and formed in the semiconductor layer, and a longitudinal transistor Tr1 in which a gate electrode is formed to be embedded in the semiconductor layer from a surface of the semiconductor layer. The photoelectric conversion unit PD1 of one layer in the photoelectric conversion units of the two layers or more is formed over a portion of the gate electrode of the longitudinal transistor Tr1 embedded in the semiconductor substrate and is connected to a channel formed by the longitudinal transistor Tr1.

Abstract: A three-dimensional (3D) memory device includes a memory stack including conductive layers and dielectric layers interleaving the conductive layers, and a channel structure extending through the memory stack along a vertical direction. The channel structure has a plurality of protruding portions protruding along a lateral direction and facing the conductive layers, respectively, and a plurality of normal portions facing the dielectric layers, respectively, without protruding along the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions and over the plurality of blocking structures, respectively. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the storage structures over the blocking structure.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: A first opening extending vertically through a dielectric stack is formed above a substrate. The dielectric stack includes vertically interleaved dielectric layers and sacrificial layers. Parts of the sacrificial layers facing the opening are removed to form a plurality of first recesses. A plurality of stop structures are formed along sidewalls of the plurality of first recesses. A plurality of storage structures are formed over the plurality of stop structures in the plurality of first recesses. The plurality of sacrificial layers are removed to expose the plurality of stop structures from a plurality of second recesses opposing the plurality of first recesses. The plurality of stop structures are removed to expose the plurality of storage structures. A plurality of blocking structures are formed over the plurality of storage structures in the plurality of second recesses.

Abstract: Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.