Abstract: An apparatus and technique is disclosed for demodulating an FM signal provided as an output from a sensor assembly. The FM signal may represent acceleration as measured by a sensor included on a rotating wheel in an attitude and heading reference system. The FM signal is demodulated and directly converted to a digital value to provide digital signal processing with improved performance characteristics. The demodulation is accomplished by detecting each FM cycle to provide a signal output at the occurrence of each cycle. A reference mark on the rotating wheel is detected for providing synchronization such that a demodulation angle of the rotating wheel can be determined. The demodulation angle is represented as a sine value which is read for each FM cycle during one sensor revolution and summed with all previous sine values detected during that one revolution. A digital output of that sum is then provided as a measurement of acceleration or other parameter along an axis of the system.
Abstract: A digital apparatus for performing minimum-shift-keying (MSK) modulation includes an oscillatory circuit which provides two frequencies related in a predetermined manner, and also includes a processing circuit which divides a stream of digital data to be transmitted into two parallel substreams, one substream comprising even numbered bits from the serial stream and the other substream comprising odd numbered bits from the serial stream. A combining circuit selects one of the frequencies provided by the oscillatory circuit according to the equivalence or divergence of the states of the digital substreams, and further provides as an output the selected frequency waveform or its inverse according to the state of one of the substreams.
April 3, 1981
Date of Patent:
September 3, 1985
The United States of America as represented by the Secretary of the Navy
Abstract: A phase-locked loop circuit comprises an oscillator, a phase comparator which compares the phase of an input signal with the phase of an oscillator signal, a detector which detects when the phase-locked loop circuit is locked within a predetermined frequency range and produces a corresponding lock detecting signal, and a filter circuit including a variable current source which produces a variable current in response to a change of state of the lock detecting signal to control the bandwidth of the filter circuit, a filter element which receives the variable current, a differential amplifier which receives the phase-compared signal, a current mirror circuit which receives the variable current from the variable current source, and a buffer circuit connected to the filter element which supplies an output signal to the oscillator to lock the frequency of the oscillator signal to the frequency of the input signal.
Abstract: To be able to recover from modes in which the oscillation of the voltage-controlled oscillator (V0) stops, the phase/frequency control circuit includes an RS flip-flop (RS) connected via two AND gates (U3, U3) to the two outputs (A1, A2) of the phase discriminator (P), which provide pulses for raising and lowering, respectively, the frequency of the voltage-controlled oscillator (V0). When the frequency/phase control circuit is out of lock, a pulse is generated with two monostable multivibrators (M1, M2) which passes through a signal selection circuit (S1) associated with the Q output of the RS flip-flop or through a signal selection circuit (S2) associated with the Q output of this flip-flop and controls the constant-current source (Q1) charging the smoothing device (G) or the constant-current source (Q2) discharging this device in such a way that the unwanted mode can be stopped by changing the control voltage of the oscillator (V0).
Abstract: An FSK demodulation circuit especially suited for integrated construction is provided. The demodulating circuit uses N counters and a counter selector circuit for sequentially switching the counters at every zero-cross point in the received FSK signal. Sensitivity of demodulation is improved by N-time zero-cross detection rather than counting the time between two adjacent zero-cross points. The FSK demodulation circuit uses a Switched Capacitor Bandpass Filter whose characteristics are changed by changing the frequency of an internal clock using simple dividing circuitry.
Abstract: A proximity switch comprising a detection coil, a first capacitor connected in parallel with the detection coil for forming a resonant circuit, an auxiliary coil, a second capacitor connected in parallel with the auxiliary coil for forming a resonant circuit, an oscillation circuit connected to the detection and auxiliary coils which are connected in series and in reverse winding directions, and an output circuit connected to the oscillation circuit for receiving variations in output generated from the oscillation circuit, the second capacitor having a capacitance larger than that of the first capacitor so that the second capacitor has a reduced low impedance at an oscillation frequency determined by the detection coil and the first capacitor.
Abstract: The modulating device reduces the number of electronic functions required for generating an SSB signal which is subjected to SSB peak-limiting in a transmitter which is selectively operable either on the upper channel or on the lower channel. By means of a mixer, the signal delivered by the peak-limiter is mixed with a signal whose frequency is double that of the local oscillator. By filtering the signal thus obtained by means of the filter which is symmetrical with the filter employed for carrying out SSB modulation, the signal to be transmitted on one of the channels is thus obtained. The signal to be transmitted on the other channel is obtained by reversing the position of the two filters.
Abstract: The gain margin of a junction FET oscillator is improved by the addition thereto of a bipolar transistor in parallel with the FET for boosting the closed loop circuit gain of the oscillator without degrading the phase noise performance of the FET. The oscillator circuit is formed by a grounded gate JFET with a feedback circuit including the internal impedance of the FET, a capacitor which couples source and drain of the FET, a capacitor which couples the FET source to ground, and a resonant circuit coupled between the drain of the FET and ground including a varactor diode for controlling the oscillating frequency and providing a circuit output. A bipolar transistor is coupled in parallel with the FET by coupling its collector to FET's drain and its emitter to the FET's source. The base of the transistor is coupled via a by-pass capacitor to circuit ground.
Abstract: According to the present invention, an FM signal is applied to a limiter through a signal input terminal to remove a noise element included in the FM signal. The limited FM signal is then supplied to a delay means for delaying the signal for a predetermined time. The delayed signal is then supplied to one of a pair of input terminals of a multiplying circuit. Either the limited FM signal or a reference potential is supplied to the other input terminal of the multiplying circuit. The multiplying circuit demodulates the FM signal which is then supplied to a low pass filter. The low pass filter transforms the demodulated signal into an analog signal which is then supplied to a signal output terminal.
Abstract: A demodulator for demodulating alternating signals modulated by pulse modulation, or by frequency modulation. The demodulator requires only a single constant current source, a single ramp voltage producing capacitor, and a sample-and-hold function. The intelligence contained in the modulated carrier is transformed into a first pulse train, and a second pulse train is produced in response to the first pulse train. The first pulse train samples and holds the ramp voltage, and the second pulse train immediately resets the ramp voltage circuit following each sample. The held voltage is a replica of the modulating signal, produced without the use of filters for removing the carrier.
Abstract: A frequency discriminator having a wide capture band is shown to comprise, in addition to a conventional phase detector having two channels fed by a signal whose frequency is to be determined (the first one of the channels containing a tuned circuit operative to shift the phase of the signal in accordance with the difference between the frequency of the signal and the center frequency of the tuned circuit and the second one of the channels containing a phase shifter operative to shift the phase of the signal by 90.degree. regardless of the frequency of the signal), a compensating circuit operative substantially to equalize the amplitudes of the signals applied to the phase detector, the compensating circuit including an amplifier in the first one of the channels to amplify the signal out of the tuned circuit, the gain of the amplifier being controlled by a signal indicative of the difference between the amplitudes of the signals fed to the phase detector.
Abstract: A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R, .theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated phase angles of the unity amplitude vectors (A, B) for each sample period of the information signal.
February 15, 1984
Date of Patent:
April 2, 1985
Carl F. Andren, William H. Mosley, Jr., David E. Sanders
Abstract: A carrier recovery circuit for use in a demodulator for a 2.sup.n -phase PSK modulated signal which comprises a phase-locked loop including a voltage-controlled oscillator (7) and an automatic frequency control (AFC) loop for avoiding the false lock phenomenon. The AFC loop is comprised of two differentiating circuits (21, 25), two mixer circuits (22, 26), and a difference circuit (27), and forms a symmetrical structure so as to exclude undesired noise, thereby carrying out a stable AFC operation.
Abstract: Control signals for switching the bandwidth of a filter in a phase locked loop are provided by comparator circuits having time delays at their inputs that vary as a function of the magnitude of changes in the outputs from a phase comparator. These variable time delays permit the comparator circuits to produce an output having a duration of the proper length in order to permit the filter to have a large bandwidth for a long enough time to permit the phase locked loop to become locked.
Abstract: A frequency modulator circuit arrangement, comprising a phase modulator (1) having a carrier signal input (2) which is fed from a carrier signal generator (18) and a modulation signal input (3) which is fed from a modulation signal input terminal (6) via an integrated circuit (7), includes a controllable frequency divider (16) in the carrier signal path through the phase modulator enabling the arrangement to operate with input modulation signals containing d.c. components without the integrator circuit output signal reaching impossibly high values. If the integrator output signal exceeds a first threshold (at terminal 26), a D-type flip-flop (27) is tripped causing a switch 28 to close, reducing the charge in the integrator capacitor (10) via a resistor (22) and hence changing the phase shift produced by the phase modulator. The division factor of the divider is simultaneously changed for one or more divisions cycles to introduce a compensating steady phase shift.
Abstract: A voltage controlled oscillator for use in a phase locked loop is provided with a first varactor circuit that responds to a control signal to set the center frequency of the oscillator, and with a second varactor circuit comprising a modulation varactor that responds to a modulation signal to cause the oscillator to produce a modulated output. The modulation sensitivity of the oscillator is made relatively constant between upper and lower center frequencies by applying a portion of the modulation signal to the first varactor circuit in addition to the control signal.
Abstract: Stray capacitance is reduced in a wideband tunable oscillator network by arranging the resonant circuit as one or more series circuit branches wherein a variable capacitance such as a varactor diode is interposed between two substantially identical inductors. In the disclosed VHF-UHF oscillator, the inductors are realized by TEM transmission lines of the stripline variety. The stripline is formed by a multilayer printed circuit board arrangement and two resonant circuit branches are interconnected in a manner that permits biasing of the varactor diodes without the use of blocking capacitors in the resonant circuit path.
Abstract: An MSK modulator having a simple construction with only a single necessary adjustment. The digital bit stream to be modulated is fed directly to the control input of a 0,.pi. phase shifter in a single-sideband modulator. A phase shift circuit is used to couple an IF signal to the IF signal input of the single-sideband modulator with the phase thereof adjusted by 0 or .pi. in response to two contiguous bits of the input data stream so as to maintain phase continuity in the output of the modulator for all possible bit combinations in the input stream.
Abstract: A mm wavelength power combiner comprising an open resonator comprising a r of confronting concave reflectors which can be either spherical or parabolic. The resonator dimensions are many times the wavelength of the energy sources to be combined. A plurality of mm wave energy sources are applied to the resonator in such a way that the great majority of the energy bounces back and forth between the reflectors near the axis thereof in the fundamental or Gaussian mode. The design minimizes multimoding and diffraction losses.
November 24, 1982
Date of Patent:
January 29, 1985
The United States of America as represented by the Secretary of the Army
Abstract: A phase locked loop is disclosed which subtracts an estimated signal from an input signal and operates upon the residual signal. The residual signal is demodulated and applied to a controlled oscillator which produces feedback signals approximately the sine and cosine of the input signal. The cosine feedback signal is multiplied by the residual signal whose resultant signal is a frequency correction signal. The sine feedback signal is multiplied by the residual signal for multiplication again by the sine feedback signal to produce the estimated signal which is amplitude and frequency controlled. This signal is then subtracted from the input signal to reduce the residual signal to near zero.
January 8, 1982
Date of Patent:
January 22, 1985
Litton Systems, Inc.
John G. Mark, James R. Steele, Craig C. Hansen