Patents Examined by Wael Fabemy
  • Patent number: 6706603
    Abstract: The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain region, implanting a layer within the epitaxial layer wherein the thickness of the layer substantially defines a channel length of the device and replacing the layer with a gate layer.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: March 16, 2004
    Assignee: Agere Systems Inc.
    Inventor: Sailesh Chittipeddi