Abstract: A method of fabricating a thin film transistor (TFT) assembly having a plurality of array lines, a plurality of pads, a plurality of link lines connecting the pads to the array lines, an insulating layer, and an electrode pattern formed on a substrate, and further having short-preventing structures for preventing electrical shorts between the pads and the link lines. The method includes the steps of forming the plurality of pads on the substrata, depositing the insulating layer on the substrate including over the pads, etching the insulating layer, to form contact holes, and etching the insulating layer between the adjacent pads to expose a surface of the substrate to prevent a short between the adjacent pads from occurring, and forming the electrode pattern on the insulating layer by depositing and patterning an electrode layer such that the electrode pattern contacts the pads through the contact holes formed in the insulating layer.

Abstract: A semiconductor device with a charge holding capacitor comprises a lower electrode connected via a plug to one of the source and drain of an MIS transistor, a capacitor insulating film formed the lower electrode, an upper electrode formed on the capacitor insulating film. The lower electrode includes a first constituting portion that is embedded in a hole in which the plug has been embedded and so formed that it self-aligns with the plug and a second constituting portion which is formed on the first constituting portion and on regions outside the fist constituting portion and whose cross section is larger than that of the first constituting portion. The first constituting portion and the second constituting portion are formed integrally by a continues film.