Patents Examined by Wael Faberyl
  • Patent number: 6686652
    Abstract: An assembly and method suitable for use in packaging integrated circuits including a support substrate for supporting an integrated circuit die embedded in a molded encapsulating cap. The substrate includes a conductive die attach pad adapted to be molded into the encapsulating cap. The pad includes an interior facing support surface and a spaced-apart exterior facing exposed surface defined by a peripheral edge. The support surface is adapted to support the embedded die, while the exposed surface is to be exposed from the encapsulating cap. The attach pad further includes a locking ledge portion extending outward peripherally beyond at least a portion of the exposed surface peripheral edge. This ledge is adapted to be subtended in the encapsulating cap in a manner substantially preventing a pull-out of the attach pad in a direction away from the encapsulating cap.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 3, 2004
    Assignee: National Semiconductor
    Inventors: Jaime Bayan, Peter H. Spalding, Harry Cheng-Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong
  • Patent number: 6670660
    Abstract: There is provided, according to one embodiment of this invention, a semiconductor memory device comprising first memory elements to store a first state or a second state according to a change in resistance value, each of the first memory elements comprising one terminal and the other terminal, the first memory elements arranged parallel with each other, a first wiring connected with the one terminal of each of the first memory elements, and a second wiring formed in parallel with the first wiring and connected with the other terminal of each of the first memory elements, wherein the first state or the second state stored in one of selected from the first memory elements is read out by delivering an electric current from one of the first and second wirings via the one of selected from the first memory elements to the other of the first and second wirings.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: December 30, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Hosotani