Patents Examined by Wael Fabmayl
  • Patent number: 6351037
    Abstract: A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 26, 2002
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ing-Ruey Liaw, Meng-Jaw Cherng