Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.

Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.

Abstract: A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material.as the first diffusion barrier layer. The first diffusion barrier layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

Abstract: A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deoinized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H2O or,ammonium hydroxide NH4OH and water H2O is applied to the periphery of the spinning wafer.

Abstract: A capacitive pressure sensor (10) utilizes a diaphragm (38) that is formed along with forming gates (56,57) of active devices on the same semiconductor substrate (11).

Abstract: A new method is provided to replace tungsten plugs for wafers that trigger the WCVD backside alarm. In this new rework process, the original TiN glue layer is sputter etched back and a new (“fresh”) 100-Angstrom thick layer of TiN is deposited. The new tungsten plug is created over the top surface of the refreshed glue layer.

Abstract: In a semicondutor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.