Patents Examined by Wael Fahmy, Jr.
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Patent number: 6541345Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.Type: GrantFiled: May 4, 1998Date of Patent: April 1, 2003Assignee: Sony CorporationInventor: Hiroshi Komatsu
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Patent number: 6534387Abstract: After a metal post 8 is formed on a semiconductor wafer 20, a groove 21 is formed in a first dicing step. The semiconductor wafer is resin-sealed by a rein layer R from its upper surface. The semiconductor wafer is ground from its lower surface to a depth reaching the bottom of the groove 21 so that the semiconductor wafer is divided into individual chips 20A. The resin layer is ground to expose the head of the metal post. After a solder ball is loaded on the metal post 8, the portion of the resin layer between adjacent chips 20A is diced in a second dicing step so that the individual chips 20A are separated from one another.Type: GrantFiled: October 6, 2000Date of Patent: March 18, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroyuki Shinogi, Ryoji Tokushige, Nobuyuki Takai
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Patent number: 6524874Abstract: In one aspect, the invention includes a method of forming field emission emitter tips, comprising: a) providing a masking material over a semiconductor substrate to form a masking-material-covered substrate; b) submerging at least a portion of the masking-material-covered semiconductor substrate in a liquid; c) providing particulates suspended on an upper surface of the liquid; d) while the particulates are suspended, moving the submerged masking-material-covered substrate relative to the suspended particulates to form tightly packed monolayer of the particulates supported on the masking material of the masking-material-covered substrate; e) decreasing a dimension of the particulates to leave some portions of the masking material covered by the particulates and other portions of the masking material uncovered by the particulates; f) after decreasing the dimension and while the particulates are supported on the upper surface, exposing the masking-material-covered substrate to first etching conditions which remType: GrantFiled: August 5, 1998Date of Patent: February 25, 2003Assignee: Micron Technology, Inc.Inventor: Jim Alwan
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Patent number: 6515340Abstract: A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.Type: GrantFiled: July 31, 2001Date of Patent: February 4, 2003Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Seizo Kakimoto, Masayuki Nakano, Kouichiro Adachi
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Patent number: 6514877Abstract: To fabricate masks for deep ultra-violet lithography and for extreme ultra-violet lithography, a layer of material opaque to deep ultra-violet radiation and an extreme ultra-violet radiation absorbent layer are each deposited successively with a layer of silicon and a layer of metal on a respective transparent substrate. A focused electron beam is displaced on the superposed layers of metal and silicon to form a structure of etch-resistant metal/silicon compound. The deep ultra-violet mask is then formed by etching the three layers to leave on the substrate, the metal/silicon compound structure with the extreme ultra-violet absorbent layer beneath it.Type: GrantFiled: October 27, 2000Date of Patent: February 4, 2003Assignee: Universite de SherbrookeInventors: Jacques Beauvais, Dominique Drouin, Eric Lavallee
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Patent number: 6500700Abstract: An object of the present invention is to provide a fabrication method of a liquid crystal display which can reduce the number of masks used in a photolithography process. According to this structure, a gate bus line and a storage capacitor wiring are formed using a first mask, and first metal films are formed on the whole surface including a sidewall insulating film. Then, etching is performed using a second mask until an active semiconductor layer in a TFT forming area on the gate bus line and in an element separation area between pixels exposes. Along with an electroplating of a metal film on the first metal films on a drain electrode, a third metal film thinner than the second metal film is formed on an active semiconductor between the drain electrode and a source electrode and to a pixel electrode except the element separation area between pixels.Type: GrantFiled: September 28, 2000Date of Patent: December 31, 2002Assignee: Fujitsu LimitedInventor: Satoru Kawai
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Patent number: 6501189Abstract: A semiconductor wafer has an alignment mark for use in aligning the wafer with exposure equipment during the manufacturing of a semiconductor device. The wafer is made by forming a chemical mechanical polishing target layer over an alignment mark layer, chemically-mechanically polishing the target layer to planarize the same, and prior to forming the chemical mechanical polishing target layer over the alignment mark layer, forming a dense pattern of lands or trenches in the alignment layer of dimensions and an inter-spacing preselected to inhibit a dishing phenomenon from occurring in the target layer as the result of its being chemically-mechanically polished. The lands or trenches may be disposed in at least a 2×2 array of rows and columns.Type: GrantFiled: December 27, 1999Date of Patent: December 31, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Young-chang Kim, Heung-jo Ryuk, Young-koog Han
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Patent number: 6486021Abstract: A semiconductor device for use in a memory cell includes an active matrix an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of lower electrodes formed on top of the conductive plugs, Ta2O5 films formed on the lower electrodes, composite films formed on the Ta2O5 films and upper electrodes formed on the composite films.Type: GrantFiled: December 4, 2000Date of Patent: November 26, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Min-Soo Kim, Chan Lim
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Patent number: 6475841Abstract: A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).Type: GrantFiled: June 2, 2000Date of Patent: November 5, 2002Assignee: Motorola, Inc.Inventors: William J. Taylor, Jr., Srikanth B. Samavedam, Nigel Cave
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Patent number: 6468860Abstract: A method for manufacturing an integrated circuit having high voltage transistors and low voltage transistors is disclosed. First, lightly doped drains are formed in both high voltage transistors and low voltage transistors within the integrated circuit. A thin layer of silicon nitrate film is then deposited on the first and second transistors. Afterwards, a layer of silicon oxide is deposited on the silicon nitride film. After forming oxide spacers on both high voltage transistors and low voltage transistors, the oxide spacers are removed from the low voltage transistors. Finally, diffusion implants are performed on the first and second transistors. As a result, the high voltage transistors possess lightly doped drained junctions.Type: GrantFiled: November 15, 2000Date of Patent: October 22, 2002Assignee: BAE Systems Information and Electronic Systems Integration, Inc.Inventors: Murty S. Polavarapu, Jon Maimon
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Patent number: 6455380Abstract: A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.Type: GrantFiled: December 14, 2000Date of Patent: September 24, 2002Assignee: LG Semicon Co., LtdInventor: Gyu Han Yoon
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Patent number: 6444578Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.Type: GrantFiled: February 21, 2001Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, Kevin K. Chan, Guy M. Cohen, Kathryn Wilder Guarini, James M. Harper, Christian Lavoie, Paul M. Solomon
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Patent number: 6432762Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.Type: GrantFiled: March 23, 2000Date of Patent: August 13, 2002Assignee: SGS-Thomson MicroelectronicsInventors: Giovanna Dalla Libera, Bruno Vajana, Roberta Bottini, Carlo Cremonesi
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Patent number: 6432844Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.Type: GrantFiled: January 11, 2000Date of Patent: August 13, 2002Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 6429095Abstract: A method of manufacturing a semiconductor article comprises forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding the first article and a second article so as to produce a multilayer structure having the porous layer in the inside thereof, and separating the multilayer structure along the porous layer.Type: GrantFiled: August 3, 2001Date of Patent: August 6, 2002Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara
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Patent number: 6423646Abstract: The present invention discloses a method for simultaneously removing from a silicon surface polymeric films and damaged silicon layers by exposing the surface to a cleaning solution that contains amine or ethanolamine for a length of time that is sufficient to remove all such unwanted materials. The method is effective in cleaning away damaged silicon layers having a thickness between about 20 Å and about 60 Å in a period of time between about 2 minutes and about 20 minutes. In a preferred embodiment, the cleaning solution is a water solution of ethanolamine and gallic acid.Type: GrantFiled: June 4, 1998Date of Patent: July 23, 2002Assignee: Vanguard International Semiconductor CorporationInventors: Tzu-Shih Yen, Hsiu-Lan Lee, Pei-Wen Li
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Patent number: 6395591Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.Type: GrantFiled: December 7, 2000Date of Patent: May 28, 2002Assignee: Micrel, IncorporatedInventors: Stephen McCormack, Martin Alter, Robert S. Wrathall, Carlos Alberto Laber
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Patent number: 6329238Abstract: In a semiconductor memory device such as a DRAM, a conductive film is arranged on the rim portion of a isolation insulating film in opposition to a semiconductor substrate with a thin insulating film in between. This conductive film is electrically connected to a lower electrode of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.Type: GrantFiled: November 21, 2000Date of Patent: December 11, 2001Assignee: Hitachi, Ltd.Inventors: Ken Yamaguchi, Shinichiro Kimura, Masatada Horiuchi, Tatsuya Teshima
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Patent number: 6329264Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and is communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer.Type: GrantFiled: May 12, 1999Date of Patent: December 11, 2001Assignee: TSMC-Acer Semiconductor Manufacturing Inc.Inventor: Shye-Lin Wu
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Patent number: 6319813Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, methods of forming such circuitry utilizing dual damascene technology, and resultant integrated circuitry constructions are described. In one embodiment, a substrate is provided having a circuit device. At least three layers are formed over the substrate and through which electrical connection is to be made with the circuit device. The three layers comprise first and second layers having an etch stop layer interposed therebetween. A contact opening is formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed relative to the etch stop layer and defines a trough joined with the contact opening. Conductive material is subsequently formed within the trough and contact opening.Type: GrantFiled: July 6, 1998Date of Patent: November 20, 2001Assignee: Micron Technology, Inc.Inventor: John H. Givens