Patents Examined by Wael Fanmyh
  • Patent number: 6365472
    Abstract: A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order to perform the ion implantation for forming the source and drain regions of the MOS transistor, impurity ions are implanted using the first and second side walls provided to the gate electrode as a mask, and then the heat treatment for impurity activation is performed after removing the second side wall near the source and drain regions doped with high-concentration impurity ions. By removing the second side wall prior to the heat treatment, the stress applied to the edges of the high-concentration impurity doped regions in an amorphous state is decreased. The defects therefore can be suppressed from being formed at the edges of the source and drain regions near the gate electrode in the recrystallization of the amorphous layer by the heat treatment.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: April 2, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunari Ishimaru, Fumitomo Matsuoka, Kaori Umezawa