Patents Examined by Walker L. Lindsay, Jr.
  • Patent number: 6680230
    Abstract: A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: January 20, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norihisa Arai, Fumitaka Arai, Seiichi Aritome, Akira Shimizu, Riichiro Shirota