Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.

Abstract: A display device according to an embodiment may include a first sub-display panel and a second sub-display panel adjacent to the first sub-display panel in a first direction. The first sub-display panel may include a first pixel adjacent to the second sub-display panel and a first ground line disposed between the first pixel and the second sub-display panel and extending in a second direction crossing the first direction. The second sub-display panel may include a second pixel adjacent to the first sub-display panel and a second ground line disposed between the second pixel and the first sub-display panel and extending in the second direction.

Abstract: One or more electronic devices that are mounted on a substrate, including at least one cooling plate in contact with the one or more electronic devices, are encapsulated. The substrate is clamped between a first mold half and a second mold half which define a molding cavity for molding the one or more electronic devices. A cavity insert movably located in the first mold half is projected into the cavity in order to contact and apply a sealing pressure onto the at least one cooling plate. After introducing a molding compound into the cavity at a first fill pressure, the molding compound in the cavity is packed by applying a second fill pressure which is higher than the first fill pressure. During this time, the sealing pressure is maintained at values that are higher than the first fill pressure and the second fill pressure.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method includes supplying a vaporized precursor into a processing volume, supplying activated elements including ions and radicals from a remote plasma source, energizing the activated elements using RF source power at a first duty cycle to react with the vaporized precursor to deposit an SiNHx film onto a substrate disposed in the processing volume, supplying a first process gas from the remote plasma source while providing RF bias power at a second duty cycle different from the first duty cycle to the substrate support to convert the SiNHx film to an SiOx film, supplying a process gas mixture formed from a second process gas supplied from the remote plasma source and a third process gas supplied from the gas supply while providing RF bias power at the second duty cycle to the substrate support, and annealing the substrate.

Abstract: A semiconductor nanosheet device including semiconductor channel layers vertically aligned and stacked one on top of another, separated by a work function metal, and a second layer between two first layers, the second layer and two first layers between the semiconductor channel layers and a substrate. A semiconductor device including a lower first layer, a second layer, and a source drain region between a first set of semiconductor channel layers vertically aligned and stacked one on top of another, and a second set of semiconductor channel layers. A method including forming a stack sacrificial layer, a stack of nanosheet layers, forming a cavity by removing the stack sacrificial layer, and simultaneously forming a first layer on an upper surface of the stack sacrificial layer, on vertical side surfaces of the set of sacrificial gates, and an upper first layer and a lower first layer in a portion of the cavity.

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

Abstract: A substrate processing apparatus includes: a substrate holder; a nozzle that ejects a processing liquid to the substrate; a conductive pipe that supplies the processing liquid to the nozzle; a ground line that connects the conductive pipe to a reference potential; a liquid receiver provided around the substrate holder and receives liquid ejected from the nozzle; and a deterioration degree measuring unit that measures a deterioration degree of conductivity of the conductive pipe. The deterioration degree measuring unit includes: a measurement liquid supply that supplies a measurement liquid to the conductive pipe; a potential difference imparting unit that imparts a potential difference between a liquid contact surface of the liquid receiver and the reference potential; and an ammeter that measures a current value of a current flowing through a charge moving path established via the measurement liquid between the liquid contact surface of the liquid receiver and the ground line.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.

Abstract: A color filter unit and a display apparatus including the same is provided, wherein the color filter unit includes an upper substrate, a first-color color filter layer, a second-color color filter layer, and a third-color color filter layer on a first surface that is a lower surface of the upper substrate, a transparent layer on the first-color color filter layer and having one or more protrusions in a direction away from the first surface, a second color quantum dot layer on the second-color color filter layer, and a third color quantum dot layer on the third-color color filter layer.

Abstract: Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

Abstract: A method for manufacturing a nitride semiconductor device includes the steps of growing a GaN channel layer on an SiC substrate using a vertical MOCVD furnace set at a first temperature using H2 as a carrier gas, and TMG and NH3 as raw materials, holding the SiC substrate having the grown GaN channel layer in the MOCVD furnace set at a second temperature higher than the first temperature using H2 as a carrier gas, the MOCVD furnace being supplied with NH3, and growing an InAlN layer on the GaN channel layer using the MOCVD furnace set at a third temperature lower than the first temperature using N2 as a carrier gas, and TMI, TMA, and NH3 as raw materials.

Abstract: A technique allows control of the etching rate at an outer periphery of a substrate being processed. A substrate support includes a substrate support portion that supports a substrate, and an edge ring support that supports an edge ring surrounding the substrate supported on the substrate support portion. The edge ring support includes a plurality of heating elements arranged in a circumferential direction of the edge ring support and a plurality of heater power feeders. Each of the plurality of heater power feeders is included in a corresponding heating element of the plurality of heating elements to provide power from an external source to the corresponding heating element.

Abstract: A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.

Abstract: A method of forming a pitch pattern is provided. The method includes forming two adjacent mandrels separated by a first distance, D1, on a substrate, and forming a first set of alternating sidewall spacers between the two adjacent mandrels. The method further includes removing the two adjacent mandrels, and forming a second set of alternating sidewall spacers and a third set of alternating sidewall spacers on opposite sides of the first set of sidewall spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.

Abstract: A wafer having a first surface, an opposite second surface, and an outer circumferential surface that includes a curved part curved outward in a protruding manner is separated into two wafers. Part of the wafer is removed along the curved part, and a separation origin is formed inside the wafer by positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the wafer inside the wafer and executing irradiation with the laser beam while the focal point and the wafer are relatively moved in such a manner that the focal point is kept inside the wafer. The wafer is separated into two wafers by an external force.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: A method for forming an active region array and a semiconductor structure are provided. The method for forming the active region array includes the steps of: providing a substrate; forming a first mask layer on a surface of the substrate, a first etched pattern being provided in the first mask layer; forming a second mask layer covering a surface of the first mask layer; forming a third mask layer having a second etched pattern on a surface of the second mask layer; forming a flank covering a sidewall of the second etched pattern; removing the third mask layer to form a third etched pattern between adjacent flanks; etching the first mask layer along the third etched pattern to form a fourth etched pattern in the first mask layer; and etching the substrate along the first etched pattern and the fourth etched pattern, to form multiple active regions in the substrate.