Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

Abstract: An LED display screen, comprising: an LED array, consisting of multiple LED light-emitting units and used for emitting a light; an optical diffusion film, provided at a light exit side of the LED array; a matrix shading frame, comprising multiple hollow shading gratings, the hollow shading gratings corresponding one-to-one to the LED light-emitting units; and a substrate, used for supporting the LED array and the matrix shading frame, where the light emitted by the LED light-emitting units, after running through the hollow shading gratings, is diffused to a viewer side via the optical diffusion film, and the LED light-emitting units emit the light towards the hollow shading gratings.

Abstract: A device (2) is formed on a main surface of a semiconductor substrate (1). A passivation film (5) covers the main surface. A metallized pattern (6) is formed on the passivation film (5) and surrounds the device (2). A sealing metal layer (7) is formed on the metallized pattern (6) and includes a corner portion (10) in a planar view. A lid (8) is bonded to the metallized pattern (6) with the sealing metal layer (7) interposed therebetween and vacuum-seals the device (2). A dummy wiring (11) is softer than the metallized pattern (6), is formed at least between an outer portion of the corner portion of the sealing metal layer (7) and the semiconductor substrate (1), and does not electrically connected to the device (2).

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: According to one embodiment, a display device includes a substrate, a plurality of pixels, a resin layer and a common electrode. The pixels include a plurality of light emitting elements arranged on the substrate and having luminous colors different from each other, respectively. The resin layer is buried in a clearance part between the plurality of light emitting elements provided in each of the pixels. The common electrode is formed of a transparent conductive material covering the resin layer. The resin layer is provided in an island-like shape in each of the pixels.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: forming a bit line over a substrate; forming a first spacer layer over and conformal to the bit line; forming a sacrificial layer over and conformal to the first spacer layer; forming a second spacer layer over and conformal to the sacrificial layer; forming a mask layer covering a lower portion of the second spacer layer; removing an upper portion of the second spacer layer; removing the sacrificial layer; and forming a third spacer layer over the first spacer layer and the second spacer layer, thereby forming a first air gap surrounded by the lower portion of the second spacer layer.

Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

Abstract: A display device includes a flexible substrate, a bonding pad, a light-emitting diode, an encapsulant, and a support structure. The bonding pad and the light-emitting diode are located on the flexible substrate. The encapsulant covers the light-emitting diode. The support structure is laterally located between the light-emitting diode and the bonding pad. The support structure has an inclined surface, and a thickness of the support structure close to the light-emitting diode is greater than the thickness of the support structure close to the bonding pad.

Abstract: A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.

Abstract: A method of manufacture of a strain gage or flexible polyimide-based resistor, the method including the steps of providing a flexible polyimide substrate, joining a conductive foil to the flexible polyimide substrate, applying a layer of photoresist to the conductive foil and thereafter, patterning the conductive foil by etching using the photoresist, wherein the method is characterized in that it includes at least one of the following steps: surface conditioning of the flexible polyimide substrate using mechanical abrasion, scrubbing of the conductive foil prior to the patterning, removal of photoresist by scrubbing following the patterning, pressurized cleaning, using deionized water, following the patterning, automated algorithmic resistance calibration and shunt trimming and forming an emulsion layer of epoxy over the conductive foil following the patterning.

Abstract: A device for implanting particles in a substrate comprises a particle source and a particle accelerator for generating an ion beam of positively charged ions. The device also comprises a substrate holder and an energy filter, which is arranged between the particle accelerator and the substrate holder. The energy filter is a microstructured membrane with a predefined structural profile for setting a dopant depth profile and/or a defect depth profile produced in the substrate by the implantation. The device also comprises at least one passive braking element for the ion beam. The at least one passive braking element is arranged between the particle accelerator and the substrate holder and is spaced apart from the energy filter.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: A method for manufacturing a stack component in which an interposer is interposed to form a space for inserting an interlayer connection pin between circuit layers to be stacked, the method includes a printing step of simultaneously printing and forming the circuit layer and the interposer side by side in a planar manner by a 3D printer, a step of mounting a circuit element on the circuit layer, a step of mounting the interposer on the circuit layer, a step of inserting the interlayer connection pin into the interposer mounted on the circuit layer, and a step of electrically connecting the circuit layer and another circuit layer by the interlayer connection pin by stacking the other circuit layer on the circuit layer via the interposer.

Abstract: A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

Abstract: The disclosed technology includes an infrared-emitting quantum dot comprising a core comprising a first semiconductor material, a shell comprising a second semiconductor material, and a gradient interface between the core and the shell. The disclosed technology also includes methods of manufacturing the same.

Abstract: A semiconductor device and cleaning system are provided. The semiconductor device includes: a device chamber, supporting column and bearing platform in the device chamber, the supporting column being configured to support the bearing platform; and an air outlet, first and second air inlet assemblies on the device chamber, the first and second air inlet assemblies being configured to introduce clean gas into the device chamber, and the air outlet being configured to discharge gas in the device chamber. The first and second air inlet assemblies are separately provided on the device chamber on the upper and lower sides of a bearing surface of the bearing platform; and one of the first and second air inlet assemblies is configured to clean the device chamber on a side of the bearing surface away from the supporting column, and other is configured to clean a gap between the supporting column and device chamber.

Abstract: A power supply conductive trace structure of a semiconductor device includes a first power supply conductive trace in a mesh form provided in a first power supply conductive trace layer, and a second power supply conductive trace provided in a redistribution layer located on or above the first power supply conductive trace to correspond in position to a conductive trace area that is a portion of the first power supply conductive trace and to be connected to the first power supply conductive trace.

Abstract: An integrated circuit includes an array of metal conducting lines in a metal layer overlying an insulation layer supported by a substrate, a first metal segment lineup having multiple metal segments in the metal layer between a first metal conducting line and a second metal conducting line in the array of metal conducting lines, and an electric circuit having a first input and a second input. The first input is connected to the first metal conducting line and the second input is connected to the second metal conducting line, and a first length of the first metal conducting line is equal to a second length of the second metal conducting line.