Abstract: A power semiconductor module includes a plurality of semiconductor switches arranged in a plurality of groups. Each semiconductor switch has a first terminal and a second terminal having a controlled path therebetween and a control terminal. A plurality of first group contacts are each connected to the first terminals of the semiconductor switches of a respective group and a plurality of second group contacts are each connected to the second terminals of the semiconductor switches of the respective group. A plurality of control group contacts are each connected to the control terminals of the semiconductor switches of the respective group. An interconnection bridge connects the control group contacts and the first group contacts of the plurality of groups. The interconnection bridge has a layer structure with a first conductive layer and a second conductive layer being separated by an insulating layer.

Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.

Abstract: The present application provides a method for manufacturing a metal gate, comprising: step 1: forming a polysilicon dummy gate on a semiconductor substrate; step 2: forming low dielectric constant sidewalls, comprising: step 21: forming a first protective layer; step 22: forming a second low dielectric constant layer; step 23: forming a third protective layer; and step 24: performing blank etching, and forming the low dielectric constant sidewalls by stacking the first protective layer, the second low dielectric constant layer, and the third protective layer on the side surfaces of the polysilicon dummy gate; step 3: forming a zeroth interlayer film; and step 4: performing gate replacement, comprising: step 41: removing the polysilicon dummy gate, and forming a gate trench; and step 42: forming a metal gate in the gate trench.

Abstract: An integrated circuit (IC) device includes at least one circuit having an input and an output, and an output connector electrically coupled to the output. The circuit further includes a plurality of transistors electrically coupled with each other between the input and the output. The output is in a first metal layer. The output connector includes a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. The second conductive pattern electrically couples the output to the first conductive pattern.

Abstract: A semiconductor light emitting device package includes: a substrate; a first semiconductor layer including first regions including a first-type semiconductor material and having a first height, and a second region disposed between the first regions and having a second height lower than the first height; an active layer including disposed in the first regions, and emitting light of a predetermined wavelength band; a second semiconductor layer disposed on the active layer and formed of a second-type semiconductor material; a third semiconductor layer disposed on the second semiconductor layer, and formed of a second-type semiconductor material different from the second-type semiconductor material of the second semiconductor layer; a transparent electrode layer including disposed on the third semiconductor layer; and a reflective electrode layer electrically connected to the transparent electrode layer, respectively, and including portions overlapping the active layer in a vertical direction and a horizontal dir

Abstract: A semiconductor device includes a cell region and a peripheral circuit region. The cell region includes gate electrode layers stacked on a substrate, channel structures extending in a first direction, extending through the gate electrode layers, and connected to the substrate, and bit lines extending in a second direction and connected to the channel structures above the gate electrode layers. The peripheral circuit region includes page buffers connected to the bit lines. Each page buffer includes a first and second elements adjacent to each other in the second direction and sharing a common active region between a first gate structure of the first element and a second gate structure of the second element in the second direction. Boundaries of the common active region include an oblique boundary extending in an oblique direction forming an angle between 0 and 90 degrees with the second direction.

Abstract: Embodiments disclosed herein include a method of setting a target profile. In an embodiment, the method comprises obtaining a first gain curve for one or more temperature sensor offsets, and obtaining a second gain curve for one or more zone multipliers. In an embodiment, the method further comprises combining the first gain curve and the second gain curve into a thermal model. In an embodiment, the method further comprises obtaining a reference data set, and using the thermal model to generate temperature sensor offsets and/or zone multipliers to apply to the reference data set in order to generate the target profile.

Abstract: A display device with a novel structure is provided. The display device includes a first substrate provided with a plurality of pixels including a display element, and a second substrate including a first conductive layer provided with a plurality of first openings. The first conductive layer has a function of an antenna capable of transmitting and receiving a radio signal. The pixel and the first opening include a region where the pixel and the first opening overlap with each other. The second substrate includes an element layer. The element layer includes a transistor. The transistor has a function of an amplifier capable of amplifying the radio signal. The transistor each includes a semiconductor layer including a metal oxide in a channel formation region. The metal oxide contains In, Ga, and Zn.

Abstract: A substrate processing apparatus includes: a substrate holder that holds and processes a substrate; a nozzle that ejects a processing liquid to the substrate held by the substrate holder; a conductive pipe connected to the nozzle and configured to supply the processing liquid to the nozzle; a processing liquid supply that supplies the processing liquid to the nozzle via the conductive pipe; a ground line that connects the conductive pipe and a reference potential; a liquid receiver provided around the substrate holder and configured to receive the processing liquid ejected from the nozzle; an electrode provided close to the liquid receiver; a voltage source configured to apply a voltage to the electrode and impart a potential difference between a liquid contact surface of the liquid receiver and the reference potential; and an ammeter configured to measure a current value of a current flowing through a charge moving path.

Abstract: A component comprising a structural element, a leadframe and a shaped body, in which component the structural element and the leadframe are enclosed at least in regions by the shaped body in lateral directions and the leadframe does not project beyond side faces of the shaped body. The leadframe has at least one first subregion and at least one second subregion which is laterally spaced apart from the first subregion, wherein the structural element is electrically conductively connected to the second subregion by a planar contact structure. Furthermore, the structural element is arranged, in plan view, on the first subregion and projects laterally beyond the first subregion at least in regions, so that the structural element and the first subregion form an anchoring structure at which the structural element and the first subregion are anchored to the shaped body. Further specified is a method for producing such a component.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: An imaging device includes a first chip. The first chip includes a first pixel and a second pixel. The first pixel includes a first anode region and a first cathode region, and the second pixel includes a second anode region and a second cathode region. The first chip includes a first wiring layer. The first wiring layer includes a first anode electrode, a first anode via coupled to the first anode electrode and the first anode region, and a second anode via coupled to the first anode electrode and the second anode region.

Abstract: In a general aspect, a semiconductor device assembly includes a direct-bonded-metal (DBM) substrate having a ceramic layer, and a first metal layer having a uniform thickness that is disposed on a first surface of the DBM substrate. The assembly further includes a second metal layer disposed on a second surface of the DBM substrate opposite the first surface. The second metal layer includes a first portion having a first thickness, and a second portion having a second thickness, the second thickness being greater than the first thickness. The second portion of the second metal layer includes a metal alloy having a coefficient of thermal expansion (CTE) in a range of 7 to 11 parts-per-million per degrees Celsius (ppm/° C.). The assembly also includes a semiconductor die having a first surface coupled with the second portion of the second metal layer.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: A vibration damping apparatus configured to damp a vibration of a target member includes a mass body, a base disposed on the target member, a support member disposed on the base and configured to support the mass body, a housing disposed on the base so as to surround the support member, an elastic member disposed so as to form a space in the housing and configured to apply a force to the support member, and a control unit configured to control a pressure of a fluid in the space by supplying the fluid to the space based on a vibration state of the target member.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: An element substrate includes an insulating substrate, electrode wiring located on the insulating substrate, a heat-dissipating member in contact with the insulating substrate, a flexible substrate electrically connected to the electrode wiring, a temperature detecting element located on the flexible substrate, and an adhesive layer. The adhesive layer is located between the temperature detecting element and an extending portion in the heat-dissipating member and between a facing surface of the flexible substrate and the extending portion in the heat-dissipating member.

Abstract: A method of dicing a wafer includes positioning the wafer with its top side on a tape material. The wafer includes a plurality of die separated by scribe streets. A first pass being a first infrared (IR) laser beam is directed at the bottom side with a point of entry within the scribe streets. The first IR laser beam is focused with a focus point embedded within a thickness of the wafer, and has parameters selected to form an embedded crack line within the wafer. The embedded crack line does not reach the top side surface. A second pass being a second IR laser beam is directed at the bottom side having parameters selected to form a second crack line that that has a spacing relative to the embedded crack line, and the second IR laser beam causes the embedded crack line to be extended to the top side surface.

Abstract: An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.