Patents Examined by Walter H Swanson
  • Patent number: 10388690
    Abstract: A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 20, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Min Jang, Jong Hyeon Chae, Joon Sup Lee, Daewoong Suh, Hyun A. Kim, Won Young Roh, Min Woo Kang
  • Patent number: 10388568
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 20, 2019
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10388670
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
  • Patent number: 10381418
    Abstract: An OLED display device includes a substrate including a display region and a pad region, a display structure in the display region on the substrate, and a pad electrode structure in the pad region on the substrate, the pad electrode structure having a first pad electrode on the substrate, a first insulation layer covering opposite lateral portions of the first pad electrode and exposing a portion of an upper surface of the first pad electrode, a second pad electrode on the first pad electrode and on the first insulation layer, the second pad electrode having a step portion where the first pad electrode and the first insulation layer are overlapped, and a third pad electrode on the second pad electrode and on the first insulation layer, the third electrode covering the second pad electrode.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin-Seock Kim, Jong-Hee Park, Bong-Won Lee, Seung-Bae Kang, Sang-Gab Kim, Jeong-Min Park, Hyun-Eok Shin
  • Patent number: 10373952
    Abstract: A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. The thickness of the gate insulating film in one of the first and second transistors is made larger than the thickness of the gate insulating film in the other one.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 6, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazushi Fujita
  • Patent number: 10374041
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yulong Li, Paul M. Solomon, Siyuranga Koswatta
  • Patent number: 10367085
    Abstract: An IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a waved contour with thinner portions and thicker portions. When the device is on, electrons flow laterally from an N+ emitter and through a channel region. Some electrons pass downward, but others pass laterally through the floating N+ well to one of the thinner portions of the floating P type well. The electrons then pass down from the thinner portions into the N? drift layer. Other electrons pass farther through the floating N+ well to subsequent, thinner electron injector portions of the floating P type well and then into the N? drift layer. The extra electron injection afforded by the waved floating well structure reduces VCE(SAT). The waved contour is made without adding any masking step to the IGBT manufacturing process.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 30, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10340339
    Abstract: A method of fabricating a semiconductor device is provided. A substrate is provided. The substrate includes a first region, a second region and a third region. An isolation structure is formed on the substrate in the first and the second region. A removing process is performed to remove the isolation structure in the first region, so as to form a first opening exposing a top surface of the substrate. A gate structure is formed on the substrate, covering a part of the substrate in the first region and a part of the isolation structure in the second region. A first doped region of a first conductive type is formed at one side of the gate structure in the first region, and a second doped region of the first conductive type is formed in the substrate in the third region.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 2, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Chin-Han Pan, Yao-Feng Huang
  • Patent number: 10332898
    Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
  • Patent number: 10333090
    Abstract: A light emitting device including an emissive material comprising quantum dots is disclosed. In one embodiment, the device includes a cathode, a layer comprising a material capable of transporting and injection electrons comprising an inorganic material, an emissive layer comprising quantum dots, a layer comprising a material capable of transporting holes, a layer comprising a hole injection material, and an anode. In certain embodiments, the hole injection material can be a p-type doped hole transport material. In certain preferred embodiments, quantum dots comprise semiconductor nanocrystals. In another aspect of the invention, there is provided a light emitting device wherein the device has an initial turn-on voltage that is not greater than 1240/?, wherein ? represents the wavelength (nm) of light emitted by the emissive layer. Other light emitting devices and a method are disclosed.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG RESEARCH AMERICA, INC.
    Inventors: Zhaoqun Zhou, Peter T. Kazlas, Mead Misic, Zoran Popovic, John Spencer Morris
  • Patent number: 10332842
    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiseok Lee, Sooho Shin, Juik Lee, Jun Ho Lee, Kwangmin Kim, Ilyoung Moon, Jemin Park, Bumseok Seo, Chan-Sic Yoon, Hoin Lee
  • Patent number: 10325845
    Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Tin Tin Wee, Trilochan Sahoo, Sunil Sukumarapillai, Arun Kumar Kodigenahalli Venkateswar
  • Patent number: 10325986
    Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 18, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
  • Patent number: 10325993
    Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
  • Patent number: 10312381
    Abstract: A stacked III-V semiconductor diode that has an n+ layer having a dopant concentration of at least 1019 N/cm3, an n? layer having a dopant concentration of 1012 N/cm3 to 1016 N/cm3, a layer thickness of 10 ?m to 300 ?m, a p+ layer having a dopant concentration of 5·1018 N/cm3 to 5·1020 cm3 and a layer thickness greater than 2 ?m, the layers following each other in the specified order, each including a GaAs compound or being made from a GaAs compound and having a monolithic design, the n+ layer or the p+ layer being a substrate, and a lower side of the n? layer being integrally connected to an upper side of the n+ layer. The stacked III-V semiconductor diode including a first defect layer having a layer thickness greater than 0.5 ?m, the defect layer being situated within the n? layer.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 4, 2019
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10312390
    Abstract: A light receiving device includes a substrate having a principal surface and a back surface including a light receiving surface; a metal wire disposed on the principal surface, the metal wire including a bonding portion having an opening; and photodiodes that is arranged in an array on the substrate, each of the photodiodes including an electrode connected to the bonding portion of the metal wire and a semiconductor mesa including a stacked semiconductor layer, the stacked semiconductor layer including a first semiconductor layer disposed on the substrate, an optical absorption layer including a type-II superlattice structure, and a second semiconductor layer. Each of the electrodes of the photodiodes is disposed on a side surface of the semiconductor mesa in contact with the first semiconductor layer. The first semiconductor layer faces to the light receiving surface through the opening of the bonding portion.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 4, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Sundararajan Balasekaran, Daisuke Kimura
  • Patent number: 10312083
    Abstract: An example embodiment includes method for forming a layer of a Group III-Nitride material. The method includes providing a substrate having a main surface comprising a layer of a first Group III-nitride material. The substrate further includes, on the main surface, a dielectric layer comprising an opening exposing the first Group III-nitride material. A thermal treatment process is performed while subjecting the substrate to a gas mixture comprising a nitrogen containing gas, thereby increasing temperature of the substrate up to a temperature for growing a layer of a second Group III-nitride material. At least one Group III-metal organic precursor gas is subsequently introduced into the gas mixture at the growth temperature, thereby forming, at least in the opening on the exposed Group III-nitride material, a layer of the second Group III-nitride material by selective epitaxial growth, characterized in that the gas mixture is free of hydrogen gas.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 4, 2019
    Assignee: IMEC VZW
    Inventors: Hu Liang, Yoganand Saripalli
  • Patent number: 10290714
    Abstract: In some embodiments, a BJT structure includes a base region, an emitter region formed in the base region and including an emitter doping region, a collector region including a collector doping region, an insulating structure and a field plate. The base region forms a junction with the collector region between the emitter and collector doping regions. The field plate is formed over an insulating structure over the junction. A first distance between the corresponding emitter and collector doping regions to the junction is shorter than a second distance in another BJT structure without the field plate corresponding to the first distance. The first distance causes a breakdown of the junction corresponding to a first breakdown voltage value between the emitter and collector doping regions being substantially the same or greater than a second breakdown voltage value of the other BJT structure corresponding to the first breakdown voltage value.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Ying Chen, Yu-Chang Jong, Shui-Ming Cheng
  • Patent number: 10290634
    Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin Peng, Min-hwa Chi
  • Patent number: 10290600
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen