Patents Examined by Walter H Swanson
  • Patent number: 11417526
    Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 16, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David L. O'Meara, Eric Chih-Fang Liu, Jodi Grzeskowiak, Anton deVilliers, Akiteru Ko, Anthony Dip
  • Patent number: 11410938
    Abstract: According to one embodiment, a semiconductor package includes a semiconductor chip, a sealing resin that has a flat plate shape and seals the semiconductor chip inside, a first electrode that includes a first mounting surface exposed on a first main face of the sealing resin, a second electrode that includes a second mounting surface exposed on the first main face, and a groove provided on the first main face. The first mounting surface includes a first end portion arranged in an inner region of the first main face and opposed to the second electrode. The groove includes a first connection portion connected to the first end portion, and a second connection portion connected to a lateral face of the sealing resin.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 9, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Miwako Suzuki
  • Patent number: 11404425
    Abstract: The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: August 2, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fang-Sheng Chou, Ching Chang
  • Patent number: 11387379
    Abstract: A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 11380553
    Abstract: The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method for fabricating the semiconductor device includes providing a target layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers. The first tilted etch process and the second tilted etch process use the second hard mask layers as pattern guides and the first hard mask layer is turned into a patterned first hard mask layer by the first openings and the second openings.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 5, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Huan-Yung Yeh
  • Patent number: 11373880
    Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christopher J Penny, Ekmini Anuja De Silva, Ashim Dutta, Abraham Arceo de la Pena
  • Patent number: 11373992
    Abstract: The disclosure provides a double patterning technology to define peripheral patterns in a DRAM cell. Due to the consideration of line width, the peripheral pattern lines need to undergo two lithographic processes and two etch processes. The presence of additional photoresist patterns in the array region while fabricating peripheral patterns on the M0 layer can increase the stability of peripheral pattern lines. Peripheral pattern lines will not collapse after being subjected to the rinse of developing agent. Moreover, the photoresist coverage of patterns in the array region is not excessive, so the loading effect during etch processes is reduced and the occurrence of photoresist residues is avoided.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 28, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Yuan Kuo, Chih-Hao Kuo
  • Patent number: 11367616
    Abstract: A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 11367618
    Abstract: A semiconductor patterning process includes the following steps. A substrate is provided, wherein the substrate has a first region, a second region, and a third region, and the second region is located between the first region and the third region. A plurality of initial mask patterns are formed on the substrate. A first mask material layer is conformally formed on the substrate. A first mask pattern is formed above at least two adjacent initial mask patterns in the second region and on the first mask material layer in between, and a second mask pattern is formed on the first mask material layer on sidewalls of remaining initial mask patterns. A portion of the first mask material layer is removed using the first mask pattern and the second mask pattern as a mask to form a final mask pattern on the substrate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 11362079
    Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, first dielectric material layers overlying the first semiconductor devices, and first metal interconnect structures, providing a second semiconductor die containing a second substrate, second semiconductor devices, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures, depositing a manganese layer on a top surface of the first dielectric material layers, disposing the second semiconductor die on the manganese layer such that a surface of the second dielectric material layers contacts the manganese layer, and performing a bonding anneal to bond the first semiconductor die to the second semiconductor die and to convert the manganese layer into a manganese-containing oxide layer, such that the manganese-containing oxide layer is bonded to the first dielectric material layers and the second dielectric material
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 14, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11361965
    Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: June 14, 2022
    Assignee: HRL Laboratories, LLC
    Inventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
  • Patent number: 11348913
    Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Lakgyo Jeong, Seolun Yang, Yongrae Cho, Hee Bum Hong
  • Patent number: 11342229
    Abstract: A method for forming an electrical connection structure is provided. The method includes forming a first metal material in an opening of a dielectric layer. The first metal material includes a plurality of grains. The method also includes forming a second metal material over the first metal material. The method also includes annealing the second metal material so that the second metal material diffuses along grain boundaries of the grains of the first metal material. The method also includes removing the second metal material from the upper surface of the first metal material.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Chun-Yuan Chen, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11327395
    Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hee Kim, Chan Hwang
  • Patent number: 11329126
    Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Tilke, Hans Weber, Christian Fachmann, Roman Knoefler, Gabor Mezoesi, Manfred Pippan, Thomas Rupp, Michael Treu, Armin Willmeroth
  • Patent number: 11322501
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 11315788
    Abstract: A process of realizing a silicon micropattern having a large aspect ratio in a semiconductor-manufacturing process, and a novel wet etching method that includes treating an organic carbon film layer so that a hydrofluoric-acid-resistant material is selectively attached to the organic carbon film layer and then wet etching the same using an aqueous solution containing hydrofluoric acid, thus forming a pattern, are proposed. In the method of forming the pattern by wet etching, etching is performed so that an active region having a depth of several ?m in an object to be etched is not damaged when a pattern having a small CD is formed, thereby exhibiting an effect of providing a method of forming a micropattern.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: April 26, 2022
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Su Jin Lee, Gi Hong Kim, Seung Hun Lee
  • Patent number: 11315887
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ying-Cheng Chuang, Chung-Lin Huang
  • Patent number: 11309183
    Abstract: A semiconductor structure and a forming method thereof are provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jin Jisong
  • Patent number: 11309396
    Abstract: A semiconductor device includes a first device formed over a substrate. The first device includes a first gate stack encircling a first nanostructure, and the first device is a logic circuit device. The semiconductor device includes a second device formed over the first device. The second device includes a second gate stack encircling a second nanostructure, and the second device is a static random access memory (SRAM).
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hao Wu, Zhi-Chang Lin, Ting-Hung Hsu, Kuan-Lun Cheng