Abstract: A film-forming composition suitable as a resist underlayer film-forming composition from which a resist underlayer film having not only a good EUV resist adhesivity but also a good etching processability due to a high fluorine-based etching rate. For example, a film-forming composition includes a polymer represented by Formula (E1) and a solvent.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.

Abstract: The application discloses a method for forming a fin structure in a fin field effect transistor process, which includes: performing photolithography and etching for a first time to form a first core layer pattern and a second core layer pattern, and depositing an etching mask layer; etching back the etching mask layer to form sidewalls of the first core layer pattern and sidewalls of the second core layer pattern; performing photolithography for a second time; etching the substrate for a first time to form fins and a planar active area consisting of a substrate material; removing sidewalls of a first photoresist pattern, a second photoresist pattern and the second core layer pattern, and reserving the second core layer pattern; performing photolithography for a third time; etching the substrate for a second time to form reference layer overlay mark and a fin cut area consisting of the substrate material.

Abstract: A method of processing a wafer includes preparing a wafer having a substrate and a silicon-containing film formed on the substrate; forming a hard mask on the silicon-containing film; forming a pattern on the hard mask by etching the hard mask; and etching the silicon-containing film using the hard mask on which the pattern is formed, wherein the hard mask has a first film formed on the silicon-containing film and containing tungsten, and a second film formed on the first film and containing zirconium or titanium and oxygen.

Abstract: A light emitting device includes: a resin package including: a resin part, and a plurality of leads including a first lead and a second lead, wherein the resin package has a concave portion having a bottom face at which a part of an upper surface of the first lead and a part of an upper surface of the second lead are exposed from the resin part; a light emitting element mounted on the bottom face of the concave portion; and a sealing member covering the light emitting element in the concave portion. The plurality of leads comprise a plurality of notch parts including a first notch part on a first side corresponding to a first outer side surface of the resin package and a second notch part on a second side corresponding to a second outer side surface of the resin package.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.

Abstract: Systems and related methods are described that can be used for etching and/or depositing materials. In some embodiments, the systems comprise an outer chamber and an inner chamber. The inner chamber can comprise a lower chamber part and an upper chamber part which are moveable with respect to each other between a closed position and an open position. The upper chamber part and the lower chamber part can abut in the closed position. The upper chamber part and the lower chamber part may further define an opening in the open position.

Abstract: A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, which includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate and includes a first active area, a second active area disposed outside the first active area, and a third active area disposed outside the second active area. The shallow trench isolation is disposed in the substrate to surround the active structure. Through the second active area and the third active of the active structure, the structural stability of the semiconductor device may be enhanced to improve the stress around the semiconductor device, thereby preventing from structural collapse or deformation.

Abstract: A method of manufacturing a semiconductor device, includes attaching a first susceptor to a film forming apparatus, measuring a magnitude of a warp of the first susceptor, setting a first initial film formation condition as a film formation condition of the film forming apparatus in accordance with the measured magnitude of the warp of the first susceptor, and placing a plurality of first wafers on the first susceptor and forming a first film on the plurality of first wafers under the film formation condition. The setting of the first initial film formation condition includes reading the first initial film formation condition from a recording medium storing a database. The database includes a plurality of pieces of data in which magnitudes of warps of susceptors are associated with initial film formation conditions for forming the first film.

Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.

Abstract: A display device includes: an array of pixels disposed on a display area; a connection pad disposed on a pad area; a transmission line electrically coupled with the connection pad; and a conductive dummy pattern disposed under the transmission line. A part of the conductive dummy pattern overlaps the transmission line in a plan view. The transmission line transmits a driving signal or a power signal to the array of pixels. The connection pad includes a pad conductive layer electrically coupled with the transmission line, and a passivation layer disposed on the pad conductive layer. The passivation layer covers at least a side surface of the pad conductive layer and defines an opening overlapping the conductive dummy pattern and the transmission line in the plan view.

Abstract: Provided are a ceramic substrate and a method of manufacturing the same, which suppress a warpage phenomenon caused by a difference in volumes occupied by upper and lower metal layers of a ceramic base material and controls areas of the upper and lower metal layers especially when thicknesses of the upper and lower metal layers on the ceramic base material are equal to each other, thereby reducing a defect rate of the ceramic substrate.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Abstract: A method for predicting an inclination angle of an etched hole can include operations as follows. A preset change range of an etching rate of an etching device for an object to be etched on a surface of a monitored sample in different operation stages is determined. An etching rate change curve of the etching device for the object to be etched on the surface of a monitored sample in a current operation stage is acquired. When the etching rate change curve exceeds the preset change range, it is determined that an inclination angle of an etched hole of an etched product currently etched by the etching device exceeds a preset angle.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A method of processing a wafer includes a groove forming step of forming grooves in the wafer to a depth equal to or larger than a thickness of chips to be produced from the wafer from a face side of the wafer along projected dicing lines, a separation initiating point forming step of positioning a focused spot of a laser at a depth in the wafer corresponding to a thickness of the chips from a reverse side of the wafer, applying the laser beam to the wafer while moving the focused spot and the wafer relatively to each other, thereby forming separation initiating points in the wafer that are parallel to the face side of the wafer and made up of modified layers and cracks, and a chip peeling step of peeling off the chips from the wafer at the separation initiating points.

Abstract: A method for preparing a flexible display substrate is provided. The method includes: forming an isolating protective film layer on a rigid substrate; forming a flexible base on the isolating protective film layer; forming a functional layer on the flexible base; and stripping the rigid substrate to form the flexible display substrate.