Patents Examined by Walter H Swanson
  • Patent number: 10879242
    Abstract: A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin of the PMOS FinFET device is formed on the first substrate having a top surface with a (100) crystal orientation, and another fin of the NMOS FinFET device is formed on the second substrate having a top surface with a (110) crystal orientation. The semiconductor device further includes a capping layer enclosing a buried bottom portion of the fin of the PMOS FinFET device, and another capping layer enclosing an effective channel portion of the fin of the PMOS FinFET device.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10871811
    Abstract: A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged along a first direction; and a metal region, at least including a first metal layer, a second metal layer and a third metal layer that are stacked, each metal layer including a first to a third strip electrodes, and strip electrodes with the same voltage potential in two adjacent metal layers are electrically coupled, wherein a routing direction of the strip electrode in the first metal layer is substantially perpendicular to the first direction.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 22, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Yan Chen, Xiaoni Xin, Le Liang, Shouyu Hong, Jianhong Zeng
  • Patent number: 10861860
    Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
  • Patent number: 10861790
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Kam-Tou Sio, Pin-Dai Sue, Ru-Gun Liu, Shih-Wei Peng, Wen-Hao Chen, Yung-Sung Yen, Chun-Kuang Chen
  • Patent number: 10861997
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10854533
    Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Hao Chen, Chin-Cheng Kuo
  • Patent number: 10832940
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
  • Patent number: 10777763
    Abstract: A novel light-emitting element is provided. Alternatively, a novel light-emitting element which can achieve both high efficiency and a long lifetime is provided. The light-emitting element includes a light-emitting layer between a pair of electrodes. The light-emitting element includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material. The second light-emitting layer includes a phosphorescent material. A difference in peak value between a first emission spectrum of light from the first light-emitting layer and a second emission spectrum of light from the second light-emitting layer is 30 nm or less.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: September 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoshi Seo
  • Patent number: 10770289
    Abstract: A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 8, 2020
    Assignee: Massachusetts Institute of Technology
    Inventor: Jeehwan Kim
  • Patent number: 10763337
    Abstract: A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
  • Patent number: 10763207
    Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Ganesh Hegde, Harsono Simka
  • Patent number: 10756044
    Abstract: A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang Hyuck Oh
  • Patent number: 10748914
    Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy, Manuj Nahar
  • Patent number: 10741707
    Abstract: Photodetectors and methods of forming the same include a first electrode. A carbon nanotube film is formed on the first electrode. A first graphene sheet is formed on the carbon nanotube film. A second graphene sheet is configured to exert an electrical field on the first graphene sheet that changes an electrical property of the first graphene sheet.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abram L. Falk, Kuan-Chang Chiu, Damon B. Farmer, Shu-Jen Han
  • Patent number: 10741627
    Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor on the substrate, an organic light emitting diode on the thin film transistor, and including a first electrode connected with the thin film transistor, and a black organic layer between the thin film transistor and the first electrode, and including a black protrusion spaced from the first electrode.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: August 11, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Soo Jung, Hyeok Jin Lee, Jun Woo Lee, Baek Kyun Jeon
  • Patent number: 10741638
    Abstract: A semiconductor device includes a doped Si base substrate, one or more device epitaxial layers formed over a main surface of the doped Si base substrate, a diffusion barrier structure, and a gate formed above the diffusion barrier structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si formed in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Robert Haase, Maximilian Roesch, Sylvain Leomant, Andreas Meiser, Bernhard Goller, Ravi Keshav Joshi
  • Patent number: 10741793
    Abstract: A method for preparing a light emitting device comprising: disposing an electron-injection layer comprising a metal oxide on a cathode, disposing a first layer adjacent the electron-injection layer, the first layer comprising a small molecule material with a bandgap of at least about 3 eV capable of blocking holes, forming an emissive layer comprising quantum dots capable of emitting blue light upon excitation at a surface of the first layer opposite the electron-injection layer; disposing a second layer comprising a material capable of transporting holes and blocking electrons with a bandgap of at least about 3 eV adjacent a surface of the emissive layer opposite the first layer, and disposing an anode over the second layer. A light-emitting device is also disclosed.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG RESEARCH AMERICA, INC.
    Inventors: Yuhua Niu, Peter T. Kazlas
  • Patent number: 10741477
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 10734611
    Abstract: The present disclosure relates to an organic light emitting diode display device including: a substrate having an emitting area and a non-emitting area; an insulating layer on the substrate, the insulating layer including a plurality of convex portions, a plurality of connecting portions and at least one wall in the emitting area, a height of the at least one wall is greater than a height of the plurality of convex portions; a first electrode on the substrate; an emitting layer on the first electrode; and a second electrode on the emitting layer, the first electrode, the emitting layer and the second electrode constituting a light emitting diode.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 4, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Hyun-Soo Lim, Kang-Ju Lee, Soo-Kang Kim, Won-Hoe Koo, Min-Geun Choi
  • Patent number: 10734347
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen