Abstract: Disclosed are semiconductor device fabricating method and semiconductor device fabricated by the same. The method includes forming on a lower mask layer first upper mask patterns and sacrificial spacers that cover sidewalls of the first upper mask patterns, forming first holes in the lower mask layer below the first upper mask patterns, forming second holes in the lower mask layer not covered by the first upper mask patterns and the sacrificial spacers, forming second upper mask patterns filling a space between the sacrificial spacers on the lower mask layer and also forming sacrificial patterns filling the first and second holes, removing the sacrificial spacers, using the first and second upper mask patterns to etch the lower mask layer, and removing the sacrificial patterns.

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Abstract: The disclosure provides a method for manufacturing shallow trench isolations, providing a substrate comprising a storage cell area and a peripheral area of a storage device; etching the upper part of the substrate of the storage cell area using a first etching process to form a first shallow trench, and filling the first shallow trench with silicon oxide using a first deposition process; and etching the upper part of the substrate of the peripheral area using a second etching process to form a second shallow trench, and filling the second shallow trench with silicon oxide using a second deposition process; wherein the depth and characteristic dimension of the first shallow trench are smaller than the depth and characteristic dimension of the second shallow trench. The disclosure can avoid the silicon dislocation defect of the peripheral area and ensure the device shape and characteristic dimension of the storage cell area.

Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns.

Abstract: A nanowire can include a first semiconductor portion, a second portion including a quantum structure disposed on the first portion, and a second semiconductor portion disposed on the second portion opposite the first portion. The quantum structure can include one or more quantum core structures and a quantum core shell disposed about the one or more quantum core structures. The one or more quantum core structures can include one or more quantum disks, quantum arch-shaped forms, quantum wells, quantum dots within quantum wells or combinations thereof.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.

Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.

Abstract: Embodiments provide method for forming a connecting pad. The method includes: providing a substrate; sequentially forming a conductive layer, a first pattern definition layer and a second pattern definition layer on a surface of the substrate; sequentially forming three groups of patterns intersecting with each other at 120° on the second pattern definition layer, an intersection portion of the three groups of patterns forming a hexagonal pattern definition structure on the second pattern definition layer; transferring the pattern definition structure downward, and etching away a portion of the first pattern definition layer, such that the remaining first pattern definition layer forms a columnar structure, wherein a bottom of the columnar structure is circular in shape under an action of an etching load effect; and etching the conductive layer by using the remaining first pattern definition layer as a mask, such that the remaining conductive layer forms a circular connecting pad.

Abstract: A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.

Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

Abstract: In described examples, a packaged semiconductor device includes a frame, a pre-fabricated interposer, and an integrated circuit die. The frame includes multiple conductive frame leads and multiple conductive connection points, as well as a hole in the frame surrounded by the frame leads and the conductive connection points. The pre-molded interposer has an external perimeter including multiple conductive interposer leads, and is for insertion into the hole. At least one of the interposer leads does not extend to the external perimeter of the interposer. The die is electrically coupled to selected ones of the frame leads and of the interposer leads. The interposer is inserted into the hole and coupled to the frame, and the frame, interposer, and die are together encapsulated by encapsulation material.

Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Abstract: The present application provides a method for improving the metal work function boundary effect in FinFET process, the method comprises steps of: depositing a first TiN layer on four fin structures. The first TiN layer has no gap between the second and the third fin structures; removing the first TiN layer up to a first distance from the midline between the second and third fin structures at the second fin structure side; depositing a second TiN layer; removing the second and first TiN layers from second fin structure. The thickness of the TiN layer at the bottom edge of the fin structure at the later structure of the ultra-low threshold voltage P-type transistor will be smaller from this process. Thus formed TiN layer is less prone to a bottom undercut during etching, thereby reducing the metal boundary effect and increasing of the threshold voltage of the device.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A method for manufacturing vias in a silicon wafer, the silicon wafer having a <110> crystal orientation, and having a <111> plane that is perpendicular to a surface of the wafer, tilted by 35.26°, the method comprising the steps of providing a mask having a rhomboidal-shaped opening onto a surface of the silicon wafer, such that edges of the rhomboidal-shaped opening line up with a <111> plane of a crystalline structure of the silicon wafer, etching a hole in the silicon wafer at the rhomboidal-shaped opening, and polishing the hole after the etching by a anisotropic etching.

Abstract: The disclosure provides a method for fabricating a semiconductor structure with strengthened patterns. The method includes forming a masking layer on the substrate, the masking layer including a peripheral region and an array region adjacent to the peripheral region; forming a first etched peripheral pattern in the peripheral region and a first etched array pattern in the array region, wherein the first etched peripheral pattern and the first etched array pattern have a top surface, a sidewall and a bottom surface, the sidewall connecting the top surface to the bottom surface; forming a second peripheral pattern on the first etched peripheral pattern and forming a second array pattern on the first etched array pattern; and etching the masking layer using the first etched peripheral pattern and the second peripheral pattern as an etching mask to form an etched masking layer in the peripheral region.

Abstract: In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.