Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: In a general aspect, a semiconductor device assembly includes a direct-bonded-metal (DBM) substrate having a ceramic layer, and a first metal layer having a uniform thickness that is disposed on a first surface of the DBM substrate. The assembly further includes a second metal layer disposed on a second surface of the DBM substrate opposite the first surface. The second metal layer includes a first portion having a first thickness, and a second portion having a second thickness, the second thickness being greater than the first thickness. The second portion of the second metal layer includes a metal alloy having a coefficient of thermal expansion (CTE) in a range of 7 to 11 parts-per-million per degrees Celsius (ppm/° C.). The assembly also includes a semiconductor die having a first surface coupled with the second portion of the second metal layer.

Abstract: An imaging device includes a first chip. The first chip includes a first pixel and a second pixel. The first pixel includes a first anode region and a first cathode region, and the second pixel includes a second anode region and a second cathode region. The first chip includes a first wiring layer. The first wiring layer includes a first anode electrode, a first anode via coupled to the first anode electrode and the first anode region, and a second anode via coupled to the first anode electrode and the second anode region.

Abstract: A vibration damping apparatus configured to damp a vibration of a target member includes a mass body, a base disposed on the target member, a support member disposed on the base and configured to support the mass body, a housing disposed on the base so as to surround the support member, an elastic member disposed so as to form a space in the housing and configured to apply a force to the support member, and a control unit configured to control a pressure of a fluid in the space by supplying the fluid to the space based on a vibration state of the target member.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: A method of dicing a wafer includes positioning the wafer with its top side on a tape material. The wafer includes a plurality of die separated by scribe streets. A first pass being a first infrared (IR) laser beam is directed at the bottom side with a point of entry within the scribe streets. The first IR laser beam is focused with a focus point embedded within a thickness of the wafer, and has parameters selected to form an embedded crack line within the wafer. The embedded crack line does not reach the top side surface. A second pass being a second IR laser beam is directed at the bottom side having parameters selected to form a second crack line that that has a spacing relative to the embedded crack line, and the second IR laser beam causes the embedded crack line to be extended to the top side surface.

Abstract: An element substrate includes an insulating substrate, electrode wiring located on the insulating substrate, a heat-dissipating member in contact with the insulating substrate, a flexible substrate electrically connected to the electrode wiring, a temperature detecting element located on the flexible substrate, and an adhesive layer. The adhesive layer is located between the temperature detecting element and an extending portion in the heat-dissipating member and between a facing surface of the flexible substrate and the extending portion in the heat-dissipating member.

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

Abstract: A problem to be solved is to reduce a leakage current between the gate and the source. Provided is a trench type FFT, where a thickness ?1 of an oxide insulating layer O1 that is closer to the inner side than a line extending upward from the outer peripheral side of a nitride insulating layer N is ½ of a thickness d of the nitride insulating layer N or more; and a thickness ?2 of an oxide insulating layer O3 between the upper end of the nitride insulating layer N and a gate region is ½ of the thickness d of the nitride insulating layer N or more.

Abstract: An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

Abstract: A semiconductor device includes: a semiconductor base body including: a p-type substrate; and an n-type first semiconductor layer; a first electrode; a second electrode; an isolation film; an insulation film; and a third electrode disposed over the insulation film. The first electrode is electrically connected to a first circuit C1 that is connected to a first power source Vin. The second electrode is electrically connected to a second circuit C2 that is connected to a second power source Vcc. The semiconductor base body further includes a p-type back gate region that is formed in at least a region of the semiconductor base body that faces the third electrode by way of the insulation film with a depth that allows the back gate region to reach the substrate. A dopant concentration of the back gate region falls within a range of 1×1010 cm?3 to 1×1015 cm?3.

Abstract: The present disclosure provides a method for preparing a memory device. The method includes forming a first bottom cell within a bottom substrate, comprising: forming a first bottom capacitor within the bottom substrate; forming a first bottom word line on the bottom substrate and extending along a first direction; and forming a first bottom channel layer surrounded by the first bottom word line. The method also includes forming a first top cell within a top substrate, comprising: forming a first top capacitor within the top substrate; forming a first top word line on the top substrate and extending along the first direction; and forming a first top channel layer surrounded by the first top word line. The method further includes forming a common bit line between the first bottom cell and the first top cell and extending along a second direction substantially perpendicular to the first direction.

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

Abstract: Discussed in an assembly substrate used in a display manufacturing method for placing semiconductor light-emitting devices to predetermined positions thereof using an electric field and a magnetic field, the assembly substrate including: a base part; a plurality of pair electrodes extending in one direction and disposed in parallel on the base part; a dielectric layer disposed on the base part to cover the plurality of pair electrodes; and partition walls disposed on the dielectric layer and defining cells at predetermined intervals along the one direction of the plurality of pair electrodes so as to overlap portions of the plurality of pair electrodes, and the semiconductor light-emitting devices being placed into the cells, respectively, wherein at least one of a recess portion and a concave and convex portion is formed on an upper surface of each of the partition walls.

Abstract: A metallic structure for an optical semiconductor device including a conductive base body having disposed thereon metallic layers in the following order: a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and an indium or indium alloy plated layer, wherein the indium or indium alloy plated layer has a thickness in a range of 0.002 ?m or more and 0.3 ?m or less.

Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a gate structure and a self-aligned contact structure. The substrate includes a source region and a drain region; the gate structure is formed on the substrate and are located between the source region and the drain region; and the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure sequentially connected in a direction perpendicular to the substrate, the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.