Abstract: There is provided a method for manufacturing a vertically structured LED capable of performing a chip separation process with ease. In the method, a light-emitting structure is formed on a growth substrate having a plurality of device regions and at least one device isolation region, wherein the light-emitting structure has an n-type clad layer, an active layer and a p-type clad layer which are disposed on the growth substrate in sequence. A p-electrode is formed on the light-emitting structure. Thereafter, a first plating layer is formed on the p-electrode such that it connects the plurality of device isolation regions. A pattern of a second plating layer is formed on the first plating layer of the device region. The growth substrate is removed, and an n-electrode is then formed on the n-type clad layer.

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract: A method of forming a polycrystalline silicon thin film with improved electrical characteristics and a method of manufacturing a thin film transistor using the method of forming the polycrystalline silicon thin film.

Abstract: A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.

Abstract: A method of forming a gate of a flash memory device, including the steps of forming a tunnel oxide film and a first polysilicon layer in an active region of a semiconductor substrate, an isolation film in the field region, a dielectric layer, a second polysilicon layer, a metal silicide film, and a hard mask film on the structure, etching the hard mask film, the metal silicide film, and a given region of the second polysilicon layer to expose the dielectric layer, stripping a top surface of the exposed dielectric layer of the active region and the field region, a part of the first polysilicon layer of the active region to form dielectric layer horns, the first polysilicon layer and a part of the dielectric layer horns of the active region, and the first polysilicon layer and the dielectric layer horns of the active region.