Abstract: Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.

Abstract: In one embodiment, a spacer layer (22) is formed overlying a gate electrode (16), which is formed on a semiconductor substrate (12). The spacer layer (22) is then etched to form a sidewall spacer (24). A scanning electron microscope (SEM) is then used to measure the width of the sidewall spacer (24). The measured value for the width of the sidewall spacer (24) is then used to adjust a subsequent integrated circuit fabrication process, such as a spacer etch process, an implant process, or an anneal process. As a result, transistors with improved drain saturation currents are fabricated.