Abstract: The invention disclosed a method and system for multi-port synchronous high voltage testing, which mainly uses two or more sets of testing circuit with variable output condition and a high voltage generator with zero intermediate voltage for synchronous high voltage testing. Therefore it is not only possible to prevent operators from electric shock but also to provide correct multi-port testing voltages so as not to cause object under test damage. The testing circuit uses a plurality sets of individual high voltage generator and a current detector for providing functions for reading and determining individual voltage and current, so that it is possible to perform several high voltage tests during a single test period and complete tests on electric products. It is therefore possible to achieve both reduction of test-time and safety of operators.

Abstract: A method to determine the systematic error of an instrument that measures features of a semiconductor wafer includes the following sequential steps. Collecting sensor data from measurement runs on front and back surfaces of a wafer while the wafer is oriented at different angles to the instrument for each run, yielding a front data set and a back data set for each angle. Then organizing the data in each set into a wafer-fixed coordinate frame. Reflecting all back surface data about a diameter of the wafer creates a reflected back data set. Subtracting the reflected back data from the front data for each wafer angle, and dividing the result by two, yields an averaged wafer shape for each load angle. Adding the reflected back data to the front data and dividing the result by two, yields an instrument signature for each load angle. The symmetric corrector is calculated by taking the average over all instrument signatures at each load angle.

Abstract: A semiconductor parallel tester is disclosed for simultaneously testing a plurality of DUTs secured to a handling apparatus. The test system includes a system controller for initiating system test signals and a pin electronics assembly responsive to the system test signals to generate test pattern signals for application to the plurality of DUTs. The system further includes a signal interface defining a plurality of direct signal paths between the handling apparatus and the pin electronics assembly.

Abstract: The pneumatic cylinder is fixed on between the lower member of the upper unit and the lower member of the lower unit. As the shaft of the pneumatic cylinder extends, the upper unit starts lowering by its own weight at first. When the upper unit reaches to the point limited by the stopper, the lower unit then starts rising and the lower unit stops in a state where the shaft has extended to its full length. In this state, the probes and are in contact with the printed wiring board as applying a specified pressure to it.

Abstract: A sensor for indicating changes in the physical presence of persons or objects and including at least two electrically conductive sheets of material that are spaced mutually apart on an electrically non-conductive carrier sheet or the like. A sensing circuit is also provided for sensing changes in the capacitance between the electrically conductive sheets.

Abstract: Absolute delay of a FTD is characterized by applying a stimulus signal to a first port of the FTD. A second port of the FTD is coupled to a delay element having a known delay and a reflective termination. A drive signal is applied to a third port of the FTD. A time domain reflection response to the stimulus signal is obtained and a signal peak within the response that corresponds to a return signal from the reflective termination is identified. Absolute delay of the frequency translation device is then extracted based on the known delay of the delay element and a time that corresponds to the occurrence of the identified signal peak. Delay versus frequency is characterized by isolating a segment of the obtained time domain reflection response that corresponds to a return signal from the reflective termination. Inverse frequency transforming the isolated segment of the time domain reflection response provides delay characteristics of the FTD versus frequency.