Abstract: A memory system includes a nonvolatile memory including a plurality of blocks, and a controller. The controller manages a plurality of streams and allocates a first erased block for which a data erase operation has been completed among the plurality of blocks as a general-purpose block. In a case where use of a first stream among the plurality of streams is started, if two or more erased blocks for which the data erase operation has been completed are included in the plurality of blocks, the controller allocates a second erased block as the write destination block corresponding to the first stream, and if two or more erased blocks for which the data erase operation has been completed are not included in the plurality of blocks, sets the first erased block as the write destination block.

Abstract: Disclosed is a graphics processor that comprises a plurality of processing cores and a cache that is operable to transfer data between the processing cores and a memory that the graphics processor has access to. Access logic is provided to control how memory accesses issued by the processing cores are distributed across the cache slices. The cache slice that is used for a memory access is determined using a function computed by the access logic based on one or more properties associated with the memory access, and the function can be changed over time to vary how memory accesses from the plurality of processing cores are distributed across the plural cache slices.

Abstract: Techniques and systems for enhanced storage system management are presented. In one example implementation, a method includes requesting pages each having physically contiguous space for buffering storage transactions issued for a set of storage drives managed by a storage application executed by the processor, and establishing space for the pages in a last level cache (LLC) of a processor. Based at least on monitored performance metrics related to the storage transactions, the method includes adjusting transaction buffers established within the pages that service each of the storage drives to modify a proportion of the LLC allotted among the transaction buffers and the processor.

Abstract: A method involves receiving, by a cache management module of a network, a first byte range of a data resource from a client device, the first byte range being of a first data segment size. The module determines that the first byte range is not stored at a network cache, identifies a second data segment size for data stored at the cache, computes a second byte range that is an integer multiple of the second data segment size and that includes the entirety of the first byte range, requests and receives the second byte range for the network data resource from a server and stores it at the cache in one or more data segments, each corresponding to the second data segment size, and sends third data from the cache to the client device, the third data corresponding to the first byte range and comprising data of the second data.

Abstract: A memory controller and data writing method are provided. The data writing method includes: obtaining and storing a first instruction sequence comprising a plurality of write instructions to a buffer memory; determining a plurality of first write instructions that satisfy preset conditions according to first information and second information of the write instructions; performing ascending order arrangement on the plurality of first write instructions to form a second instruction sequence; according to the second instruction sequence, sequentially executing each first write instruction so as to write sequential write data into a rewritable non-volatile memory module.

Abstract: Presented herein are systems and methods for configuring devices with write operations. One or more processors can identify a first sequence of write operations to configure a device. Each write operation in the first sequence of write operations can identify a set of a value and an address to which to write the value. The one or more processors can determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations. The one or more processors can generate a second sequence of write operations based at least on the one or more distances. The one or more processors can cause the device to be configured using the second sequence of write operations.

Abstract: A method of cache management for a code load is provided. In some embodiments, a method includes receiving a request to load code at a cluster complex. The cluster complex comprises a first node and a second node. The first node includes a first cache and the second node having a second cache. The method comprises, in response to the request, destaging the first cache of the first node and directing input/output requests to the second node. The method comprises, in response to the first cache being destaged, sending the request to the first node. The method comprises executing the request at the first node. The method comprises resuming input/output requests to the first node.

Abstract: An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the valid bit.

Abstract: A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.

Abstract: An apparatus includes a processing system including one or more memories and one or more processors coupled to the one or more memories. The processing system is configured to send, to a memory device, a first request associated with a first physical address of the memory device. The first physical address is in accordance with a first address selection scheme that includes an address hashing scheme. The processing system is further configured to send, to the memory device, a second request associated with a second physical address of the memory device. In accordance with the second request being associated with process-in-memory (PIM) operations by the memory device, the second physical address is in accordance with a second address selection scheme different than the first address selection scheme.

Abstract: An integrated circuit includes first and second memory controller circuits and a load balancing multiplexer circuit that redirects a first read operation from the first memory controller circuit to the second memory controller circuit in response to receiving an indication that the second memory controller circuit has available memory bandwidth. A circuit system includes first and second memory devices, first and second memory controller circuits, and a load balancing multiplexer circuit that sends a write operation to the first memory controller circuit to store data in the first memory device and to the second memory controller circuit to store the data in the second memory device, while performing a number of memory traffic shaping operations.

Abstract: Disclosed herein are system, method, and computer program product embodiments for transforming backups of applications. An embodiment operates by extracting a resource snapshot into memory. The resource snapshot is formatted in a first configuration. An embodiment performs a transformation on the resource snapshot, thereby transforming the resource snapshot from the first configuration to a second configuration for an environment into which the resource snapshot is being restored. The transformation is made up of a set of operations. One of the operations includes a regular expression. Once the transformation is complete, the resource snapshot is restored to the environment based on the second configuration.

Abstract: The present disclosure provides a resource allocation method, performed by a memory management unit in a resource allocation system, including: in response to a memory obtaining request forwarded by a switch in the resource allocation system, obtaining a required memory capacity and a memory start address carried by the memory obtaining request; selecting a target memory module that matches the required memory capacity from at least two memory modules in the resource allocation system based on a memory allocation unit in the resource allocation system; and performing address translation on the target memory module based on a memory address router in the memory allocation unit and the memory start address, and allocating the target memory module after the address translation to the target host.

Abstract: The present application relates to systems and methods for providing high bandwidth connections between memory and computing units. For example, memory units can be configured to perform concurrent read and write operations in parallel to one another. The memory units can also be configured to alter the relative bandwidths that are available for the read and write operations. For example, bi-directional transmission interfaces of a memory unit can be assigned to operate as uni-directional interfaces that are a part of either a data input path or a data output path.

Abstract: A cloud-based data protection service is disclosed. In an embodiment, the data protection service may support backup of data sets from one or more sites associated with one or more organizations. In an embodiment, deduplication of backup data across multiple sites of an organization and/or multiple sites associated with different organizations may be supported. In an embodiment, backup data may be post-processed in the cloud to insert fingerprints corresponding to data blocks that did not change since a previous backup was performed, to scan the backup for security threats such as viruses, other malware, personally identifiable information, etc. In an embodiment, restore may be supported from the cloud, where restore blocks may be larger than backup data blocks. In another embodiment, restore may be based on blocks that have changed since the most recent backup (or a user-selected backup).

Abstract: A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input/output interface and executes the one or more layers.

Abstract: An active drop scheme is selected from multiple drop schemes based on the active drop scheme having an associated drop request. The active drop scheme is associated with a first flash translation layer (FTL) table. A drop group is selected based on the active drop scheme. The drop group includes multiple segments of the first FTL table. The drop group is flushed to a memory device. Mapping information for the drop group is updated in a second FTL table based on flushing the drop group to the memory device.

Abstract: A method for managing data protection includes monitoring, by a data protection service, data protection requests issued by a set of client devices to obtain telemetry data, wherein the set of client devices are associated with a geographic location, performing a resource analysis on the telemetry data to determine a centralized backup system (CBS) instance allocation for a CBS instance in the geographic location, making a determination, based on the resource analysis, that the CBS instance is to be instantiated in the geographic location, based on the determination, deploying the CBS instance in a production environment located in the geographic location, and initiating a replication of backup data from a CBS to the CBS instance.

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval, a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value, and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

Abstract: In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.