Patents Examined by Wei Ma
  • Patent number: 12717726
    Abstract: An apparatus includes a processing system including one or more memories and one or more processors coupled to the one or more memories. The processing system is configured to send, to a memory device, a first request associated with a first physical address of the memory device. The first physical address is in accordance with a first address selection scheme that includes an address hashing scheme. The processing system is further configured to send, to the memory device, a second request associated with a second physical address of the memory device. In accordance with the second request being associated with process-in-memory (PIM) operations by the memory device, the second physical address is in accordance with a second address selection scheme different than the first address selection scheme.
    Type: Grant
    Filed: February 20, 2025
    Date of Patent: August 25, 2026
    Assignee: Qualcomm Incorporated
    Inventors: Rui Cao, Subbarao Palacharla, Pan Deng, Pankaj Deshmukh, Jungwon Suh
  • Patent number: 12717733
    Abstract: An integrated circuit includes first and second memory controller circuits and a load balancing multiplexer circuit that redirects a first read operation from the first memory controller circuit to the second memory controller circuit in response to receiving an indication that the second memory controller circuit has available memory bandwidth. A circuit system includes first and second memory devices, first and second memory controller circuits, and a load balancing multiplexer circuit that sends a write operation to the first memory controller circuit to store data in the first memory device and to the second memory controller circuit to store the data in the second memory device, while performing a number of memory traffic shaping operations.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: August 25, 2026
    Assignee: Altera Corporation
    Inventors: Przemek Guzy, Sheran Cardoza, Shan Liu
  • Patent number: 12710891
    Abstract: Disclosed herein are system, method, and computer program product embodiments for transforming backups of applications. An embodiment operates by extracting a resource snapshot into memory. The resource snapshot is formatted in a first configuration. An embodiment performs a transformation on the resource snapshot, thereby transforming the resource snapshot from the first configuration to a second configuration for an environment into which the resource snapshot is being restored. The transformation is made up of a set of operations. One of the operations includes a regular expression. Once the transformation is complete, the resource snapshot is restored to the environment based on the second configuration.
    Type: Grant
    Filed: October 28, 2024
    Date of Patent: August 18, 2026
    Assignee: Kasten, Inc.
    Inventors: Aaron H. Alpar, Thomas Manville, Eric William Hamilton, Vaibhav Kamra, Niraj Tolia
  • Patent number: 12711065
    Abstract: The present disclosure provides a resource allocation method, performed by a memory management unit in a resource allocation system, including: in response to a memory obtaining request forwarded by a switch in the resource allocation system, obtaining a required memory capacity and a memory start address carried by the memory obtaining request; selecting a target memory module that matches the required memory capacity from at least two memory modules in the resource allocation system based on a memory allocation unit in the resource allocation system; and performing address translation on the target memory module based on a memory address router in the memory allocation unit and the memory start address, and allocating the target memory module after the address translation to the target host.
    Type: Grant
    Filed: December 6, 2024
    Date of Patent: August 18, 2026
    Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Tao Zhang
  • Patent number: 12705202
    Abstract: The present application relates to systems and methods for providing high bandwidth connections between memory and computing units. For example, memory units can be configured to perform concurrent read and write operations in parallel to one another. The memory units can also be configured to alter the relative bandwidths that are available for the read and write operations. For example, bi-directional transmission interfaces of a memory unit can be assigned to operate as uni-directional interfaces that are a part of either a data input path or a data output path.
    Type: Grant
    Filed: August 1, 2024
    Date of Patent: August 11, 2026
    Assignee: Google LLC
    Inventors: Horia Alexandru Toma, Gurushankar Rajamani, Sukalpa Biswas, Robert S. Sprinkle
  • Patent number: 12695804
    Abstract: A cloud-based data protection service is disclosed. In an embodiment, the data protection service may support backup of data sets from one or more sites associated with one or more organizations. In an embodiment, deduplication of backup data across multiple sites of an organization and/or multiple sites associated with different organizations may be supported. In an embodiment, backup data may be post-processed in the cloud to insert fingerprints corresponding to data blocks that did not change since a previous backup was performed, to scan the backup for security threats such as viruses, other malware, personally identifiable information, etc. In an embodiment, restore may be supported from the cloud, where restore blocks may be larger than backup data blocks. In another embodiment, restore may be based on blocks that have changed since the most recent backup (or a user-selected backup).
    Type: Grant
    Filed: March 18, 2025
    Date of Patent: July 28, 2026
    Assignee: Commvault Systems, Inc.
    Inventors: Lawrence Jaemyung Chang, Woon Ho Jung, Poojan Kumar, Monoreet Mutsuddi, Amber Palekar, Hung Hing Pang, Kaustubh Sambhaji Patil, Rishabh Sharma
  • Patent number: 12675421
    Abstract: A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input/output interface and executes the one or more layers.
    Type: Grant
    Filed: October 23, 2024
    Date of Patent: July 7, 2026
    Assignee: Lattice Semiconductor Corporation
    Inventors: Satheesh Chellappan, Raghunandan Chaware
  • Patent number: 12664091
    Abstract: An active drop scheme is selected from multiple drop schemes based on the active drop scheme having an associated drop request. The active drop scheme is associated with a first flash translation layer (FTL) table. A drop group is selected based on the active drop scheme. The drop group includes multiple segments of the first FTL table. The drop group is flushed to a memory device. Mapping information for the drop group is updated in a second FTL table based on flushing the drop group to the memory device.
    Type: Grant
    Filed: December 13, 2024
    Date of Patent: June 23, 2026
    Assignee: Micron Technology, Inc.
    Inventor: Andrei Konan
  • Patent number: 12664057
    Abstract: A method for managing data protection includes monitoring, by a data protection service, data protection requests issued by a set of client devices to obtain telemetry data, wherein the set of client devices are associated with a geographic location, performing a resource analysis on the telemetry data to determine a centralized backup system (CBS) instance allocation for a CBS instance in the geographic location, making a determination, based on the resource analysis, that the CBS instance is to be instantiated in the geographic location, based on the determination, deploying the CBS instance in a production environment located in the geographic location, and initiating a replication of backup data from a CBS to the CBS instance.
    Type: Grant
    Filed: April 26, 2024
    Date of Patent: June 23, 2026
    Assignee: Dell Products L.P.
    Inventors: Pankaj Pande, Mengze Liao
  • Patent number: 12656963
    Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval, a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value, and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.
    Type: Grant
    Filed: December 11, 2024
    Date of Patent: June 16, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhwi Park, Junyoung Ko, Jungmin Bak
  • Patent number: 12650938
    Abstract: In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.
    Type: Grant
    Filed: September 16, 2024
    Date of Patent: June 9, 2026
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Noam Eshel-Goldman, Yael Rozin, Moshe Bachar, Rami Zemach
  • Patent number: 12645618
    Abstract: A host-originated memory read request is received by a non-host device from a host device to retrieve data stored at a device memory attached to the non-host device, the memory host-originated read request from the host device including a specific host-assigned memory read request type attribute. Responsive to receiving the host-originated memory read request, the non-host device generates a device-memory-bound memory read request corresponding to the host-originated memory read request, a priority mapping being applied to map the specific host-assigned memory read request type attribute to a specific device-memory priority selected from among a plurality of device-memory priorities. The device-memory-bound memory read request is sent along with the specific device-memory priority to a memory controller of the device memory to access the data stored at the device memory.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: June 2, 2026
    Inventor: Subbarao Arumilli
  • Patent number: 12645602
    Abstract: In some implementations, there is provided a method that includes configuring a first threshold for page-loadable data at a buffer cache associated with a database; checking the buffer cache to determine usage of the buffer cache by the page-loadable data; in response to the usage of the buffer cache being more than the first threshold, causing a background job to release one or more buffers in the buffer cache; checking, after releasing at least one buffer of the buffer cache, the buffer cache to determine whether usage by the page-loadable data is below the first threshold; in response to the usage being below the first threshold, stopping the release of additional one or more buffers in the buffer cache; and in response to the usage being above the first threshold, continuing the release of the additional one or more buffers in the buffer cache.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: June 2, 2026
    Assignee: SAP SE
    Inventors: Nishant Vijayvergiya, Amit Pathak, Sebastian Seifert, Thomas Peh, Sergej Hardock
  • Patent number: 12639217
    Abstract: A memory system includes a non-volatile memory and a controller that is configured to: write N pieces of address translation information repeatedly in a first block according to a first order; write the N pieces of address translation information repeatedly in a second block of the non-volatile memory according to a second order that is offset from the first order by N/2; write an update log in the first and second blocks each time one of the N pieces is written; and in response to power to the memory system being restored after shutdown, read from the first block, N/2 pieces of address translation information and N/2 update logs last written thereinto, read from the second block, N/2 pieces of address translation information and N/2 update logs last written thereinto, and reconstruct a logical-to-physical address translation table from the information read from the non-volatile memory.
    Type: Grant
    Filed: August 30, 2024
    Date of Patent: May 26, 2026
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Yuki Sasaki, Kensaku Yamaguchi
  • Patent number: 12639239
    Abstract: The memory system may include a processor; a scratch pad memory connected to the processor through an internal bus, a memory controller connected to the processor through the internal bus, and configured to access a memory device through an external bus in response to a memory access request by the processor; and a hint managing module configured to manage a hint for selecting data to be overridden on the scratch pad memory from among data loaded in the memory device.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: May 26, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeyeong Lee, Bumgyu Park, Jong-Lae Park, Min-Young Joe, Eunok Jo
  • Patent number: 12638580
    Abstract: A method for facilitating the collection of sensor data and vehicle data captured by one or more sensors of a vehicle is provided. The method includes storing sensor data and vehicle data to a portable memory device coupled to a port of a compute system of a vehicle and determining a storage capacity level of the portable memory device. In response to determining that the storage capacity level of the portable memory device has been reached, the method further includes generating one or more notifications indicating that the portable memory device that the storage capacity level of the portable memory device has been reached. The method thus includes transmitting the one or more notifications to a remote central computing system.
    Type: Grant
    Filed: July 8, 2024
    Date of Patent: May 26, 2026
    Assignee: Lyft, Inc.
    Inventors: Alfred Charles Jones, II, Marco Antonio MarroquĂ­n, Kevin Danford
  • Patent number: 12632394
    Abstract: Aspects of the disclosure are directed to cache memory management. In accordance with one aspect, the disclosure includes a shared cache memory configured to store data into a plurality of cache lines; and a client coupled to the shared cache memory, the client configured to determine if a local staling state of one of the plurality of cache lines is inactive or active.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: May 19, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Varun Jindal, George Patsilaras, Vivekanandan Naveen
  • Patent number: 12625801
    Abstract: The present disclosure relates to data processing methods, computer devices, and non-transitory computer-readable storage media. In an example method, at least one processor obtains an instruction sequence of an application program, identifies an execution sequence of read/write instructions in the instruction sequence based on the instruction sequence, and executes the read/write instructions based on the identified execution sequence.
    Type: Grant
    Filed: June 7, 2024
    Date of Patent: May 12, 2026
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Rutao Zhang, Di Yu, Kai Hou
  • Patent number: 12625704
    Abstract: A method, computer program product, and computer system for reading data stored in a set associative cache. A cache read instruction that did not read the cache after being previously launched is relaunched after an effective address (EA) of the instruction was ascertained. A hash of the ascertained EA (EAHash) and a class congruence class (CCC) is determined from the ascertained EA. A search is performed for a match of the EAHash and CCC of the ascertained EA to the EAHash and CCC, respectively, of an instruction whose EAHash, CCC, and set are stored in an instruction history stream. If the match is found, only read enables associated with the stored set of the match, which is a read enable of only one class of one address group in the cache, are activated. If the match is not found, all read enables of the one address group are activated.
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: May 12, 2026
    Assignee: International Business Machines Corporation
    Inventors: David A. Hrusecky, Wolfgang Penth
  • Patent number: 12619559
    Abstract: There is provided a smart storage device. The smart storage device comprises an accelerator which is connected to a host device through a smart interface, and includes a first model distributed from the host device, and a non-volatile memory which includes learning data used for learning the first model, wherein the accelerator learns the first model by using the learning data on the basis of a first weight and a first bias that are set in advance, provides the host device with a first output value which is output by inputting the learning data into the first model, and learns the first model by using the learning data, on the basis of a second weight and a second bias calculated from the host device with reference to the first output value.
    Type: Grant
    Filed: July 2, 2024
    Date of Patent: May 5, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Soo-Young Ji