Abstract: A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input/output interface and executes the one or more layers.

Abstract: An active drop scheme is selected from multiple drop schemes based on the active drop scheme having an associated drop request. The active drop scheme is associated with a first flash translation layer (FTL) table. A drop group is selected based on the active drop scheme. The drop group includes multiple segments of the first FTL table. The drop group is flushed to a memory device. Mapping information for the drop group is updated in a second FTL table based on flushing the drop group to the memory device.

Abstract: A method for managing data protection includes monitoring, by a data protection service, data protection requests issued by a set of client devices to obtain telemetry data, wherein the set of client devices are associated with a geographic location, performing a resource analysis on the telemetry data to determine a centralized backup system (CBS) instance allocation for a CBS instance in the geographic location, making a determination, based on the resource analysis, that the CBS instance is to be instantiated in the geographic location, based on the determination, deploying the CBS instance in a production environment located in the geographic location, and initiating a replication of backup data from a CBS to the CBS instance.

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval, a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value, and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

Abstract: In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.

Abstract: A host-originated memory read request is received by a non-host device from a host device to retrieve data stored at a device memory attached to the non-host device, the memory host-originated read request from the host device including a specific host-assigned memory read request type attribute. Responsive to receiving the host-originated memory read request, the non-host device generates a device-memory-bound memory read request corresponding to the host-originated memory read request, a priority mapping being applied to map the specific host-assigned memory read request type attribute to a specific device-memory priority selected from among a plurality of device-memory priorities. The device-memory-bound memory read request is sent along with the specific device-memory priority to a memory controller of the device memory to access the data stored at the device memory.

Abstract: In some implementations, there is provided a method that includes configuring a first threshold for page-loadable data at a buffer cache associated with a database; checking the buffer cache to determine usage of the buffer cache by the page-loadable data; in response to the usage of the buffer cache being more than the first threshold, causing a background job to release one or more buffers in the buffer cache; checking, after releasing at least one buffer of the buffer cache, the buffer cache to determine whether usage by the page-loadable data is below the first threshold; in response to the usage being below the first threshold, stopping the release of additional one or more buffers in the buffer cache; and in response to the usage being above the first threshold, continuing the release of the additional one or more buffers in the buffer cache.

Abstract: A memory system includes a non-volatile memory and a controller that is configured to: write N pieces of address translation information repeatedly in a first block according to a first order; write the N pieces of address translation information repeatedly in a second block of the non-volatile memory according to a second order that is offset from the first order by N/2; write an update log in the first and second blocks each time one of the N pieces is written; and in response to power to the memory system being restored after shutdown, read from the first block, N/2 pieces of address translation information and N/2 update logs last written thereinto, read from the second block, N/2 pieces of address translation information and N/2 update logs last written thereinto, and reconstruct a logical-to-physical address translation table from the information read from the non-volatile memory.

Abstract: The memory system may include a processor; a scratch pad memory connected to the processor through an internal bus, a memory controller connected to the processor through the internal bus, and configured to access a memory device through an external bus in response to a memory access request by the processor; and a hint managing module configured to manage a hint for selecting data to be overridden on the scratch pad memory from among data loaded in the memory device.

Abstract: A method for facilitating the collection of sensor data and vehicle data captured by one or more sensors of a vehicle is provided. The method includes storing sensor data and vehicle data to a portable memory device coupled to a port of a compute system of a vehicle and determining a storage capacity level of the portable memory device. In response to determining that the storage capacity level of the portable memory device has been reached, the method further includes generating one or more notifications indicating that the portable memory device that the storage capacity level of the portable memory device has been reached. The method thus includes transmitting the one or more notifications to a remote central computing system.

Abstract: Aspects of the disclosure are directed to cache memory management. In accordance with one aspect, the disclosure includes a shared cache memory configured to store data into a plurality of cache lines; and a client coupled to the shared cache memory, the client configured to determine if a local staling state of one of the plurality of cache lines is inactive or active.

Abstract: The present disclosure relates to data processing methods, computer devices, and non-transitory computer-readable storage media. In an example method, at least one processor obtains an instruction sequence of an application program, identifies an execution sequence of read/write instructions in the instruction sequence based on the instruction sequence, and executes the read/write instructions based on the identified execution sequence.

Abstract: A method, computer program product, and computer system for reading data stored in a set associative cache. A cache read instruction that did not read the cache after being previously launched is relaunched after an effective address (EA) of the instruction was ascertained. A hash of the ascertained EA (EAHash) and a class congruence class (CCC) is determined from the ascertained EA. A search is performed for a match of the EAHash and CCC of the ascertained EA to the EAHash and CCC, respectively, of an instruction whose EAHash, CCC, and set are stored in an instruction history stream. If the match is found, only read enables associated with the stored set of the match, which is a read enable of only one class of one address group in the cache, are activated. If the match is not found, all read enables of the one address group are activated.

Abstract: There is provided a smart storage device. The smart storage device comprises an accelerator which is connected to a host device through a smart interface, and includes a first model distributed from the host device, and a non-volatile memory which includes learning data used for learning the first model, wherein the accelerator learns the first model by using the learning data on the basis of a first weight and a first bias that are set in advance, provides the host device with a first output value which is output by inputting the learning data into the first model, and learns the first model by using the learning data, on the basis of a second weight and a second bias calculated from the host device with reference to the first output value.

Abstract: Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented.

Abstract: Disclosed are techniques for storing data decompressed from the compressed pages of a memory block when servicing data access request from a host device of a memory system to the compressed page data in which the memory block has been compressed into multiple compressed pages. A cache buffer may store the decompressed data for a few compressed pages to save decompression memory space. The memory system may keep track of the number of accesses to the decompressed data in the cache and the number of compressed pages that have been decompressed into the cache to calculate a metric associated with the frequency of access to the compressed pages within the memory block. If the metric does not exceed a threshold, additional compressed pages are decompressed into the cache. Otherwise, all the compressed pages within the memory block are decompressed into a separately allocated memory space to reduce data access latency.

Abstract: Systems and methods include determination of caching requirements associated with an application, automatic determination of a caching strategy based on the caching requirements and metadata describing a plurality of available caches, providing the caching strategy to the application, and execution of the application to cache data based on the caching strategy.

Abstract: This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.

Abstract: Apparatuses, systems, and techniques to perform multi-threaded memory allocation in parallel by one or more software programs being performed on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, one or more software programs expressed in part by code using an application programming interface for parallel computing, such as CUDA, perform allocation, search, and deallocation of memory efficiently and in parallel on a GPU.

Abstract: An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.