Abstract: A computer method, system and program product for debugging and/or monitoring an instruction set and having an improved breakpoint handling mechanism involving a hardware debug register set (or like breakpoint register means). Instead of patching a break instruction into a debuggee instruction sequence, re-inserting the original instruction and then single stepping through that instruction before replacing it with the patch, the original instruction is left in place and continuous execution is resumed. Before resuming however, the breakpoint register is set so that the break instruction can be re-applied while a flag (eg the Intel RF flag) is set so as to prevent a hardware break before that is desired.