Abstract: An audiographics conferencing arrangement for use in a business communication system allows the conferees to exchange displayed text and/or graphics stored locally in their respective data terminals. The conferees may change the displayed text and/or graphics and such changes are automatically distributed to the other data terminals so that all of the conferees view the same information. Moreover, a data terminal and its associated telephone station set may be included in an audiographics conference connection even though they are not directly served by the business communication system. In addition, one of the conferees may establish concurrent with the original audiographics conference connection a second audiographics conference connection with one or more other data terminals and transfer information obtained from one conference connection to the other conference connection.

Abstract: A local area network which is multi-path in nature and uses many small programmed nodes interconnected by low bandwidth cables with a typical data transfer rate of 9600 BPS. Connections between pairs of devices on the network are obtained by a flooding technique at the start of communications which is performed by a network control program resident in each node. Data transmitted between devices connected to the network is packetized and routed through the network via the nodes identified by the flooding operation. Packet transmission through node output ports is buffered and multiplexed so as to reduce degradation in response time by heavy traffic monopolizing a node output port.

Abstract: A time division multiplex transmission system includes: a time division multiplex encoder for supplying a master clock to a plurality of PCM digital signal sources having a same sampling requency and a same quantization bit number to effect clock synchronization and generating a time-divisionally multiplexed data signal based on a data word not D/A converted and sampled from each digital signal source; a transmission line for transmitting the multiplexed data signal from the time division multiplex encoder; and a time division demultiplex decoder for selecting a desired transmitted, multiplexed data signal and demultiplexing the selected data signal in accordance with a transmission rate before the time division multiplexing.

Abstract: A method and apparatus is described for transmitting and receiving data signals and voice band signals over a single pair of wires, wherein the energy content of the data signals in the voice bands is transferred to a higher frequency to avoid interference between the two. This is accomplished by sinusoidally encoding the data pulses in the frequency domain. The encoding is equivalently performed in the time domain by linearly combining weighted delayed and advanced versions of the data pulses, in accordance with a weighting formula. A transversal filter is used to multiple delayed and advanced versions of the data pulses by a scaling factor times the ratio of m!/(m-i)!i! factorial wherein i is the ith version being weighted, m is an integer greater than one and ! indicates the factorial function.

Abstract: An architecture for a switching node of a communication network includes a dedicated hardware Layer 1 processing portion and a Layer 2 and 3 processing portion based on multiple programmed general purpose processors. An array of such processors are used with an arbitration scheme for selecting which of the processors is to be used for any given Layer 2 or Layer 3 process. The architecture allows the node's capacity to be expanded by simply adding more processors to handle increased traffic.

Abstract: A communication network has one master node which maintains an active master list (AML) containing the node addresses of all nodes to which the token will be passed. When nodes are added or deleted from the network, it is efficient in terms of data bus occupancy and individual processing time by the nodes if the successor address for each node is broadcast in a single message, and the availability of an AML makes this possible. The network has the capability of efficiently updating the AML whenever the configuration of the network is so changed.

Abstract: A universal asynchronous receiver-transmitter (UART) (54) is dislosed which is compatible with an industry standard yet provides additional features. The UART can be selectably operated in a synchronous or an asynchronous mode. First-in, first-out (FIFO) registers (404,424) are provided for both the receiver and transmitter portions of the UART, and a parity error and special character recognizer unit (412) on the receive side flags characters when they are placed in the reveive FIFO. Reception of a special character or one with a parity error is reported to the user via an interrupt mechanism (430). A random access memory (RAM) (413) with the special character recognized stores user-supplied patterns which are recognized as special characters. User-accessible status and control registers (408) have bit positions which enable and control the enhanced functions of the UART while maintaining compatability with the industry standard.

Abstract: With the switching node at least one coupling element is associated which has a number n of input lines and n output lines optionally connectible to the input lines via a space switch with a buffer store being assigned to the input lines in which k data packets occurring sequentially on the particular input line are storable before being routed further to the output lines indicated by the address signals contained in the particular data packet. The buffer stores have each a plurality m.ltoreq.k output terminals via which simultaneously m data packets stored in the particular buffer store and to be routed further to m different output lines are suppliable to a space switch having m.times.n input terminals and n output terminals.

Abstract: A tester for local networks of the carrier sense multiple access and collision detection type with a bus architecture transmission system. The network includes at least one elementary segment comprising a number of stations. The tester includes a transmission and reception circuit analagous to those of the stations, including, in addition, a collision generating device which emits a data frame when it has received from the encoding and decoding circuit associated with the transmission and reception circuit, a signal indicating the presence of a transmission of a frame by some station other than itself, and a transmission request from the transmission control circuit, this transmitted frame being received by the encoding and decoding circuit.

Abstract: This circuit is a trunk type interface circuit which interfaces between duplicate copies of an ISDN system and T-carrier facilities. The circuit is controlled by a digital signal processor which has a 16-bit wide data bus. The digital signal processor is capable of supporting various Zero Byte Time Slot Interchange (ZBTSI) techniques. Also included is an administrative microprocessor which collects data concerning the operation of the trunk circuit and transmits this information to the ISDN system. The administrative microprocessor also receives information from currently unused data bits in the input bit stream from the ISDN system. The trunk circuit includes one receiver which collects and stores data transmitted by the ISDN system. Another receiver collects and stores data transmitted via the T-carrier facilities. The trunk circuit also includes two transmitters. One transmitter converts previously formatted data to T-carrier compatible data and transmits the data via the T-carrier facilities.

Abstract: The switching device includes a multiplexer (2) and a control device (8). The multiplexer has a first input (Y.sub.i) for receiving a first digital signal (S1), a second input (Y.sub.j) for receiving a second digital signal (S2), an output to emit a resultant digital signal (SR), and at least one control input. The control device send signals to the multiplexer's control inputs for switching the multiplexer from the first input to the second input and to introduce during the switching a characteristic sequence into the multiplexer output. This sequence may, in particular, be produced by a clock signal generator connected to a third input of the multiplexer.

Abstract: A plurality of multiplexer cells are connected in series to accommodate the multiplexing of different data and channels. Pairs of variable lengths shift registers are utilized in each multiplexer cell in order to accommodate different data rates. One of the shift registers is always connected in series with the multiplex data stream while the other is connected to receive and store channel data. The two registers are alternately connected to baseband data stream and channel data in order to accomplish the multiplexing function.

Abstract: In a TDMA radio communication system consisting of a master station and a plurality of slave stations, the master station performs channel control for sending time slot assignment information to only a calling slave station in response to a time slot assignment request from a calling slave station.The calling slave station performs transmission control. In this control, the calling slave station detects an address of a destination device from an input transmitting signal, determines a called slave station based on the detected address, adds the address of the called slave station to the input transmitting signal to form a transmission signal, and inserts the transmission signal in the assigned time slot.

Abstract: A repeater station receives from a preceding station a first downward signal of a frame period, with a propagation delay. The repeater transmits a second downward signal to a succeeding station, which second signal is a delayed repeat of the first downward signal. A first delay circuit in the repeater gives the first downward signal a fixed delay which is equal to an integral submultiple of the frame period minus the propagation delay and precesses the second downward signal to include the fixed delay. The first downward signal includes a reference signal and a number signal which is representative of the repeater station. A first detector detects the reference signal. When a second detector detects the number signal, an internal delay circuit gives the detected reference signal an internal delay which depends on the number signal and produces a delayed reference signal.

Abstract: System and method for regulating the servicing of multiple peripheral devices by a central processing unit. The system and method is highly beneficial where some of the peripheral devices place equal priority demand on the central processing unit. A plurality of link interfaces are interconnected between the peripheral devices and the central processing unit. The link interfaces are interconnected by means of token transmission circuitry. The token transmission circuitry requlates the operation of the link interfaces and thereby the serving of the peripheral devices. The use of the token transmission circuitry substantially increases the efficiency and performance of the link interfaces.

Abstract: An information delivery system which continuously provides sets of information which can be selected by a user. Digital data is encoded as analog signals which are used to amplitude modulate a carrier signal. A plurality of such modulated carrier signals, each constituting a subchannel, are mixed together to form a single channel which can be delivered to a user over a cable or otherwise. The data provided on each carrier in the channel constantly repeats itself so that the entire set of data on a particular carrier wll be available to a user in a relatively short time regardless of the time of access by the user. A first subchannel contains an index to the remaining subchannels to allow user selection of a particular set of information.

Abstract: A packet distribution network including a distributed arrangement for selecting packets based on the availability or unavailability of packet destinations is disclosed. A plurality of input units receive and store packets before distribution. Each input unit also receives a sequence of addresses representing packet destinations and a sequence of usage indicators each describing the availability or unavailability of an associated one of the destination addresses. The sequence of addresses and the associated usage indicators are provided to the input units such that the address of each packet destination is contemporaneously received by only one input unit. Each input unit selects a stored packet based on the received destination addresses and associated usage indicators and marks previously available destinations unavailable to other input units by modifying the usage indicator associated with a packet destination for which a packet is selected.

Abstract: A signal distribution cable network in which a plurality of information channels are defined by respective carrier frequencies and serve a plurality of local signal sources (SS1, SS2, SS3) and signal destination receivers (SR1, SR2, SR3) connected to the network. The network has a channel allocation controller (CT) which operates on request to allocate temporarily an unused channel for transporting signals from a local signal source (SS1, SS2, SS3) to a signal destination receiver (SR1, SR2, SR3). The controller (CT) transmits tuning signals to the local signal source and the signal destination receiver to tune them to the carrier frequency of the allocated channel. The channel allocation excludes channels which normally carry signals from external signal sources.

Abstract: A simple adapter for multiplexing ISDN (Integrated Services Digital Network) terminals adapter for an ISDN basic subscriber access system is connected by a connector to a subscriber's point-to-multipoint bus. The adapter allows a greater number of terminal equipment (TE) to be connected to the point-to-multipoint bus via S/T interfaces. By checking the type, subaddress or the like of a call coming in through the adapter, the adapter is capable of limiting the kind of acceptable calls.

Abstract: A packet data switch for transferring data packets including an address part and an information part from one of a plurality of incoming data links (10,30,50) to one or more outgoing data links (22, 42, 62) and supplying new address information for each data packet on the outgoing links. The selector includes a separate memory means (e.g. 13) for each incoming data link (10, 30, 50) and a separate memory means (e.g. 20) for each outgoing data link (22, 42, 62). The memory means assigned to the incoming data links send control signals for selective writing of a data packet into one or more buffer registers (e.g. 19) which are each assigned to an outgoing link (e.g. 22). The memory means assigned to the outgoing links supply the new address information for the data packets to the outgoing links.