Abstract: In a TDMA/TDD transmitter, a control data generation unit receives assignment terms for a number of time slots and slot data from an external source, produces a set of assignment control data according to the assignment terms and the slot data and stores the set of assignment control data into an entry of a control data table in response to a transfer command signal. A sequence controller analyzes sets of assignment control data maintained in the control data generation unit and produces a number of address pointers. The address pointers are stored in an address pointer table in such a sequence that they can be sequentially read out in a desired transmission sequence. The aforesaid transfer command signal is supplied from the sequence controller to the control data generation unit in response to each of the address pointers.

Abstract: A method for processing a call in an asynchronous mobile communication system including an asynchronous mobile station, an asynchronous radio network, wherein a synchronous core network is interlocked, includes the steps of: setting up the call in case a calling call message is generated in the mobile station; establishing a channel between the asynchronous mobile station and the asynchronous radio network; handling basic information for assigning a radio resource; performing a cipher establishment; establishing the radio resource; performing a configuration for a service; and transmitting a phone call stand-by message to a user.

Abstract: A multiport switching device includes an Internal Rules Checker (IRC) that determines forwarding addresses for packets received at the device. The determined forwarding addresses may include a new MAC destination address that is to substituted for the MAC destination address of the received packet. In one implementation, the new MAC destination address is transmitted from the IRC to the dequeuing logic by transmitting pairs of adjacent words through the switch output queues. In other implementations, the new MAC destination address is transmitted from the IRC to the dequeuing logic by transmitting an index field to the output queuing logic or by having the IRC write the new MAC destination address directly to memory.

Abstract: A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The architecture further includes a synchronization buffer in each input signal path for transferring the input signal to the clock rate of the time slot interchanger. The architecture permits greater levels of integration when the time slot interchanger has more inputs than outputs, and/or the time slot interchanger provides the output signal to a pointer processor to transfer the output signal to the clock rate of the output signal path.

Abstract: In an Internet facsimile apparatus, a facsimile controller temporarily stores data received from a G3 (Group 3) facsimile apparatus or the other terminal unit to communicate with. A packetizer/depacketizer packetizes the data sequentially read out in accordance with size information fed from a size information storage and feeds the resulting packets to a UDPTL controller and a buffer. The packetizer/depacketizer determines whether data received from the other terminal unit and decoded is a response to data sent from the G3 facsimile apparatus or retransmitted data, and delivers a response detection signal representative of the result of decision to the UDPTL controller. In the UDPTL controller, a filtering circuit deletes stored past data in accordance with the response detection signal representative of a response. The apparatus reduces a load on an IP (Internet Protocol) network.

Abstract: Techniques to determine the rate for a data transmission in an OFDM system. The maximum data rate that may be reliably transmitted over a given multipath (non-flat) channel by the OFDM system is determined based on a metric for an equivalent (flat) channel. For the given multipath channel and a particular rate (which may be indicative of a particular data rate, modulation scheme, and coding rate), the metric is initially derived from an equivalent data rate and the particular modulation scheme. A threshold SNR needed to reliably transmit the particular data rate using the particular modulation scheme and coding rate is then determined. The particular rate is deemed as being supported by the multipath channel if the metric is greater than or equal to the threshold SNR. Incremental transmission is used to account for errors in the determined data rate.

Abstract: A method for allocating a bandwidth between a plurality of network terminals (NTx) coupled, via a common link (L), to a main network station (LT) in a communication network. A medium access controller (MC) forwards permits to the network terminals, each permit containing a terminal identifier and allowing a predetermined share of bandwidth. It comprises two sets of counters, each set including one counter (Gx or Fx) for each terminal. The bandwidth is split into a guarantee bandwidth that is shared by operating the first set of counters and an excess bandwidth that is shared by operating the second set of counters. The guaranteed bandwidth is allocated according to fixed weights, and the excess bandwidth is also allocated according to weights. The weights for the excess bandwidth are either fixed or varying according to the load status of the terminals.

Abstract: Methods, apparatuses and systems directed to measuring delay attributable to a network. The network delay is computed, in one implementation by determining a round-trip time for a network connection based on the arrival times of selected packets transmitted by first and second endpoints to establish the network connection, measuring the time gaps between consecutively increasing data packets in an ordered packet stream associated with a transaction, comparing the measured time gaps to the round-trip time, and computing a network delay for the transaction by adding the round-trip time to the measured time gaps that exceed the round trip time.

Abstract: A method for adaptively partitioning a buffer in a shared buffer switch is provided. The buffer partitioning method for a shared buffer switch which has a plurality of input ports, a plurality of output ports, and a shared buffer, the method for determining whether or not to store a cell, which is newly received through one of the input ports, in the shared buffer comprises the steps of (a) determining a buffer area of the shared buffer in which the newly received cell is stored; (b) determining a cell discard threshold with respect to the total number of cells stored in the shared buffer and the changing rate, with respect to time, of the total number of the cells; and (c) determining whether or not to store the newly received cell in the shared buffer, by comparing the number of cells stored in the buffer area in which the newly received cell is to be stored, with the cell discard threshold.

Abstract: A high integrity process is provided to apply pilot phase rates to call processing decisions. An estimate or measurement of the rate of change of a pilot's PN phase offset is used to assist in making CDMA call processing decisions. The phase rate is a measure of the rate of change of a pilot's PN phase offset relative to a mobile time reference and is directly related to the multipath environment and movement of the mobile. Both an integrity algorithm to compute an integrity indicator and a technique to apply the integrity indicator to predict future pilot strengths are included.

Abstract: A router device and a cut-through path control method capable of carrying out the load balancing at an intermediate router device which actually has a multi-path information, without requiring a special processing at the edge router are disclosed. At a router device at which multi-path exists, one router among a plurality of routers that can possibly be a next hop router is selected so as to contribute to a load balancing, according to a whole or a prescribed part of information regarding a state of cut-through path set up in which the router device is involved, at a time of setting up a cut-through path in the multi-path, and a prescribed control for setting up the cut-through path with that one router as the next hop router is carried out.

Abstract: A network processing device includes multiple control processors or applications. One or more of the multiple processors generates an address resolution request. A network interface is adapted to detect a reply to the address resolution request and broadcast the detected address resolution reply to the multiple control processors in the network processing device.

Abstract: The multiple access communication system according to the invention comprises at least one primary station (2) and a plurality of secondary stations (32, 34, 36). The primary station (2) and the secondary stations (32, 34, 36) are interconnected via a network, e.g. a coaxial cable network or a hybrid fiber/coax network. The secondary stations (32, 34, 36) can transmit return signals in a return signal frequency band to the primary station (2). However, the secondary stations (32, 34, 36) are arranged for transmitting the return signals in only a part of the return signal frequency band containing relatively little noise, e.g. the upper part of the return signal frequency band. The network comprises means (40) for mapping the return signals of the secondary stations (32, 34, 36) onto the full return signal frequency band, e.g. by means of a frequency converter (48, 50).

Abstract: A SCADA communication apparatus is made up of a set of modules, a first one of which is adapted for communication with a remote terminal unit (RTU), a second one of which is adapted for communication with a communications transceiver, and a third one of which is adapted for routing messages between and to physically house the first and second ones of the modules. Optionally, encryption and/or data compression can be provided by the operating system associated with the communication apparatus; or, these features may be provided in the form of application programs.

Abstract: A mechanism is provided for supporting differentiated services (quality of service) in a radio network. A radio access system is provided which supports the quality of service in data packet transmission over its air interface. The system comprises a selection of predefined default radio flows having different quality of service characteristics and means (4, 52) for selecting a radio flow having appropriate quality of service characteristics for the packet to be transmitted over the air interface from the selection.

Abstract: A line card provides terminating resistors for a bus or traces on a backplane. The line card terminations are activated (connected to ground) by a crossbar switch that is set according to programming (software/firmware/flash memory stored instructions) maintained on the line card to set the state of the resistive terminations. The programming maintained on the line card may be downloaded to the card into nonvolatile storage. The decision to utilize a specific line card to terminate or leave the bus unterminated is made by a control unit that sends command messages to the line card. A polling device interrogates each line card and sets the physically last card on the bus as a terminating card. The command messages are in ADSL Provisioning Message format and transmitted to each line card via a CPU Cell Data Link (CCDL).

Abstract: A technique for allowing a first and second group of users to share access to a communication channel such as a radio channel. A first group of users is typically a legacy group of users such as those using digital CDMA cellular telephone equipment. The second group of users are a group of data users that code their transmissions in different formats optimized for data functionalities. The first group of users share one modulation structure such as, on a reverse link, using unique phase offsets of a common pseudorandom noise (PN) code. The second group of users share another modulation structure but in a manner that is consistent and compatible with the users of the first group. Specifically, the users of the second group may all use the same PN code and code phase offset. However, they are uniquely identified such as, for example, assigning each of them a unique orthogonal code.

Abstract: The invention discloses a CDMA soft handover method which can be used in present code division multiple access systems. The invention preserves current soft handover mechanisms triggered by a pilot signal strength variation measured by a mobile station. At the same time it introduces a communication quality indication parameter—continuous error frame indication measured by mobile station. Both function together to launch and to activate system soft handover. Without changing present soft handover processes, soft handover performance is improved, possibility of lost conversation is decreased and communication quality is raised.

Abstract: The invention comprises a system and method for transmitting and receiving between voice switches compressed multiplexed packets. The invention efficiently utilizes a Digital Signal Level Zero (DS0) to provide multiplexed voice traffic between two voice switches.

Abstract: A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.