Abstract: A half-bridge having semiconductor switch elements embedded in a modular layer system that comprises a contact plane and a metal plating for establishing contact with the semiconductor switch elements, wherein the signal connections and power connections are located on a first surface of the substrate, wherein the modular layer system, signal connections and power connections are cast in a casting compound, wherein external sections of the power connections and/or signal connections formed in the conductor frame each extend from the casting compound, from a second surface that is orthogonal to the first surface, wherein the external sections each have an end that is perpendicular to the first surface.

Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

Abstract: A system for controlling the non-product wafer includes the following: a monitoring module, configured to monitor the state of the non-product wafer; a statistics module, configured to obtain usage information of the non-product wafer; and a control module, configured to receive a production instruction and control the non-product wafer according to the state and the usage information of the non-product wafer. The disclosure implements the purpose of automatic control and management of the non-product wafer.

Abstract: With respect to a method of depositing a silicon nitride film on a surface of a substrate, the method includes depositing the silicon nitride film on the surface of the substrate by intermittently supplying trisilylamine into a processing chamber accommodating the substrate.

Abstract: A substrate processing apparatus includes: a rotation support table capable of supporting and rotating a substrate; a chemical liquid nozzle that is arranged above an outer edge portion of the substrate that is supported by the rotation support table, and through which a chemical liquid is applied to the outer edge portion; and a solidified film forming unit that is arranged at least either on an upper side or on a lower side of the outer edge portion of the substrate that is supported by the rotation support table, and on a downstream side, in a direction of rotation of the substrate, of a position where the chemical liquid nozzle is arranged, and solidifies the chemical liquid applied to the outer edge portion, to form a solidified film that forms a part of an annular film.

Abstract: A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

Abstract: A carbon film deposition method includes supplying a carbon-containing gas and a halogen gas to a substrate to deposit a carbon film on the substrate by using chemical vapor deposition, and supplying a gas that reacts with halogens constituting the halogen gas to reduce the halogens contained in the carbon film. A cycle including the supplying of the carbon-containing gas and the halogen gas and the supplying of the gas that reacts with the halogens is repeated a plurality of times.

Abstract: A micro LED display panel is provided. The micro LED display panel includes a driving substrate and a plurality of bonding pads disposed on the driving substrate and spaced apart from each other. The micro LED display panel also includes a plurality of micro LED structures electrically connected to the bonding pads. Each micro LED structure includes at least one electrode disposed on the side of the micro LED structure facing the driving substrate. The electrode has a normal contact surface and a side contact surface. The normal contact surface faces the driving substrate, and the side contact surface is laterally connected to the corresponding bonding pad.

Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

Abstract: A method includes: generating a contaminant distribution map by sampling an environment of a cleanroom; selecting a first fabrication tool of the cleanroom by comparing the contaminant distribution map with at least one diffusion image in a first database; comparing parameters of the first fabrication tool against process utility information in a second database; and when the parameters are consistent with the process utility information, taking at least one action. The one action may include moving a cleaning tool to a location associated with a contaminant concentration of the contaminant distribution map; turning on a fan of the cleaning tool; stopping pod transit to the first fabrication tool; or halting production by the first fabrication tool.

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

Abstract: A semiconductor package includes a second semiconductor die stacked on a first semiconductor die. The first semiconductor die includes a first contact pad connected to a first integrated circuit, and includes a second contact pad connected to a third contact pad by a first interconnection line. The second semiconductor die includes a fourth contact pad connected to the third contact pad and connected to a second integrated circuit. A first bonding wire is connected to the first contact pad, and a second bonding wire is connected to the second contact pad.

Abstract: A light-emitting diode manufacturing method including the forming of three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, each having a lower portion and a flared upper portion inscribed within a frustum of half apical angle ?. The method further comprises, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor layer of the III-V compound covering the active area by vapor deposition at a pressure lower than 10 mPa, by using a flux of the group-III element along a direction inclined by an angle ?III and a flux of the group-V element along a direction inclined by an angle ?V with respect to the vertical axis, angles ?III and ?V being smaller than angle ?.

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

Abstract: The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. The method for manufacturing a semiconductor structure includes the following steps: providing a substrate, and forming a stabilizing layer on the substrate; forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures; forming a hard mask layer covering the stabilizing structure; forming a mask pattern connected to a top of the linear structure and an inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate.

Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.

Abstract: A gas-permeable package lid of a chip package structure and a manufacturing method thereof are provided. The gas-permeable package lid of the chip package structure includes a lid body, a through hole, and a hydrophobic gas-permeable membrane. The lid body is integrally formed. The through hole penetrates the lid body. The hydrophobic gas-permeable membrane is bonded to the lid body and shields the through hole. A part of the hydrophobic gas-permeable membrane is embedded in the lid body.

Abstract: Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.