Abstract: Provided herein is a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a contact pattern including a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, a lower conductive pattern having a hole into which the vertical contact part is inserted, and an upper conductive pattern overlapping a portion of the lower conductive pattern. The upper conductive pattern includes a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.

Abstract: An electronic device is provided. The electronic device includes an optical sensing module that includes an optical sensor array. The optical sensor array includes at least one optical sensor, at least one transparent layer disposed on the optical sensor array, and a microlens array. The microlens array includes at least one microlens and is disposed on the transparent layer.

Abstract: According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Abstract: A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip, a ring-shaped wall, and a light-permeable layer. The substrate has a first surface and a second surface that is opposite to the first surface. The first surface of the substrate has a chip-bonding region and a connection region that surrounds the chip-bonding region, and the substrate has a plurality of protrusions arranged in the connection region. The sensor chip is disposed on the chip-bonding region of the substrate and is electrically coupled to the substrate. The ring-shaped wall is formed on the connection region of the substrate, and the protrusions of the substrate are embedded in and gaplessly connected to the ring-shaped wall. The light-permeable layer is disposed on the ring-shaped wall, and the light-permeable layer, the ring-shaped wall, and the substrate jointly define an enclosed space therein.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.

Abstract: A method for forming a HEMT is disclosed. A substrate is provided. A buffer layer, a channel layer on the buffer layer, a barrier layer on the channel layer, and a semiconductor gate layer on the barrier layer are formed on the substrate. A metal gate layer is formed on the semiconductor gate layer. A spacer is formed on sidewalls of the metal gate layer. The semiconductor gate layer is then etched by using the spacer and the metal gate layer as an etching mask. A passivation layer is then formed to cover the barrier layer, the semiconductor gate layer and the metal gate layer. An opening is formed in the passivation layer to expose the metal gate layer. A gate electrode is formed on the passivation layer and in direct contact with the metal gate layer.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A light emitting device including: a substrate; a light emitting element on the substrate, and having a first end and a second end in a longitudinal direction; first and second banks on the substrate and spaced apart from each other with the light emitting element interposed therebetween; a first electrode on the first bank and adjacent to the first end of the light emitting element; a second electrode on the second bank and adjacent to the second end of the light emitting element; a first contact electrode coupling the first electrode and the first end of the light emitting element, and a second contact electrode coupling the second electrode and the second end of the light emitting element. When viewed on a plane, the first electrode partially overlaps the first bank, and the second electrode partially overlaps the second bank.

Abstract: A semiconductor device includes: a substrate; a first connection structure disposed on the substrate, the first connection structure Including a first connection conductor; a transistor disposed between the substrate and the first connection structure; a first bonding structure Including a first bonding pad connected to the first connection conductor; a second bonding structure including a second bonding pad connected to the first bonding pad; a second connection structure including a second connection conductor connected to the second bonding pad; a stack structure disposed on the second connection structure; a channel structure penetrating the stack structure; and a chip guard penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip guard surrounding the stack structure and the channel structure.

Abstract: In one aspect, a method includes depositing a first glass layer on a metallization layer and depositing an etch stop layer on the first glass layer. The method further includes depositing a second glass layer on the etch stop layer and polishing the second glass layer down to at least a surface of the etch stop layer.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method for a 3D NAND memory device includes providing a substrate, forming at least one contact pad over a first portion of a face side of the substrate, forming memory cells over a second portion of the face side of the substrate, depositing a first dielectric layer to cover the at least one contact pad and the memory cells of, forming a first connecting pads over the first dielectric layer and connected to the at least one contact pad and the memory cells, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Abstract: A light-emitting layer of a light-emitting element contains halogen ligands and organic ligands coordinated to each of quantum dots. The light-emitting layer includes: a first region toward a hole-transport layer; and a second region toward an electron-transport layer. In the first region, a concentration of the halogen ligands is higher than a concentration of the organic ligands, and, in the second region, the concentration of the halogen ligands is lower than the concentration of the organic ligands.

Abstract: The present technology relates to an imaging element and an electronic apparatus which make it possible to acquire a variety of information regarding a subject including polarization information. Included are an organic photoelectric conversion film that has a light-transmitting property, is oriented in a predetermined axial direction, and includes a step; an upper electrode arranged on a light incident surface side of the organic photoelectric conversion film; and a lower electrode arranged on a side of the organic photoelectric conversion film facing the upper electrode. Protrusions and recesses are formed on the light incident surface side of the organic photoelectric conversion film. An accumulation layer that accumulates an electric charge converted by the organic photoelectric conversion film is included between the organic photoelectric conversion film and the lower electrode, and the step is formed depending on the presence or absence of the accumulation layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.

Abstract: An array substrate includes: a base; light shield layers and a first auxiliary electrode that are disposed on the base; at least one insulating layer covering the light shield layers and the first auxiliary electrode; first electrodes that are disposed on the at least one insulating layer, a conductive connection portion; a pixel definition layer defining light-emitting regions and covering the conductive connection portion; organic light-emitting layers disposed on the first electrodes and located in the light-emitting regions defined by the pixel definition layer; and at least one second electrode covering the pixel definition layer and the organic light-emitting layers. A second electrode is electrically connected to the conductive connection portion through a via that penetrates through the pixel definition layer. The conductive connection portion is electrically connected to the first auxiliary electrode through a via that penetrates through the at least one insulating layer.