Patents Examined by William B Partridge
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Patent number: 12040432Abstract: Described are light emitting diode (LED) devices comprising a mesa with semiconductor layers, the semiconductor layers including an N-type layer, an active layer, and a P-type layer. A patterned transparent conductive oxide layer is on the top surface of the mesa. The patterned transparent conductive oxide layer has a first portion with a first thickness and a second portion with a second thickness, the second thickness less than the first thickness. Optical loss of the LED is reduced in the thinned region of the transparent conductive oxide layer.Type: GrantFiled: March 5, 2021Date of Patent: July 16, 2024Assignee: Lumileds LLCInventors: Jeffrey DiMaria, Erik William Young
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Patent number: 12021137Abstract: A method of forming a semiconductor device may include depositing a NiAl layer on a substrate, oxidizing the NiAl layer to form a bilayer including a NiO semiconducting material layer and an AlOx layer on the NiO semiconducting material layer, forming a semiconductor layer including the NiO semiconducting material layer, the semiconductor layer also including a channel region, and forming a gate dielectric on the channel region of the semiconductor layer.Type: GrantFiled: January 19, 2022Date of Patent: June 25, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Oreste Madia
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Patent number: 12021105Abstract: A pixel array includes octagon-shaped pixel sensors and square-shaped pixel sensors. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. Moreover, the pixel array may include a combination of red, green, and blue pixel sensors to obtain color information from incident light; yellow pixel sensors for blue and green color enhancement and correction for the pixel array; near infrared (NIR) pixel sensors to increase contour sharpness and low light performance for the pixel array; and/or white pixel sensors to increase light sensitivity and brightness for the pixel array. The capability to configure different sizes and types of pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.Type: GrantFiled: November 20, 2020Date of Patent: June 25, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Kuo-Cheng Lee, Cheng-Ming Wu
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Patent number: 12010924Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.Type: GrantFiled: March 18, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Pin Chiu, Chang-Lin Yang, Chien-Hua Huang, Chen-Chiu Huang, Chih-Fan Huang, Dian-Hau Chen
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Patent number: 11996420Abstract: An image sensor is provided. An image sensor includes: a substrate including an active pixel sensor region, an optical black sensor region, and a boundary region provided between the active pixel sensor region and the optical black sensor region; a photoelectric conversion element provided inside the substrate on the boundary region; a passivation layer provided on the substrate; a grid trench formed on the boundary region of the substrate and extending from an upper surface of the passivation layer toward an inside of the passivation layer; grid patterns, each of the grid patterns being provided on the passivation layer on each of the active pixel sensor region and the boundary region of the substrate, at least a part of a grid pattern being provided inside the grid trench; and a color filter provided between the grid patterns.Type: GrantFiled: August 18, 2021Date of Patent: May 28, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Seok Kim, Byung Jun Park, Hyeon Ho Kim, Young Woo Chung
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Patent number: 11835989Abstract: Implementations described herein identify and exploit opportunities for offloading search-time and/or index-time operations to programmed offloading hardware accelerators (POHAs). An event-based data intake and query system is implemented in an enterprise core that is in communication with the POHAs over network interfaces. The system receives search requests associated with search-time operations classified into off-loadable operations and non-off-loadable operations. Non-off-loadable operations are distributed to local processing resources, and off-loadable operations are distributed to the POHAs for offloaded processing. The system can post-process both the locally processed and offload-processed results to generate search results responsive to at least some of the received search requests.Type: GrantFiled: April 21, 2022Date of Patent: December 5, 2023Assignee: SPLUNK Inc.Inventors: Warren Shum, Zefu Dai
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Patent number: 11803508Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.Type: GrantFiled: July 26, 2022Date of Patent: October 31, 2023Assignee: quadric.io, Inc.Inventors: Nigel Drego, Aman Sikka, Ananth Durbha, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
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Patent number: 11797473Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.Type: GrantFiled: October 8, 2018Date of Patent: October 24, 2023Assignee: Altera CorporationInventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
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Patent number: 11789739Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.Type: GrantFiled: May 3, 2021Date of Patent: October 17, 2023Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Glenn Ashley Farrall
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Patent number: 11789735Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.Type: GrantFiled: May 25, 2021Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Vedvyas Shanbhogue, Jason W. Brandt, Uday R. Savagaonkar, Ravi L. Sahita
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Patent number: 11775294Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.Type: GrantFiled: November 30, 2021Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Peng Gu, Krishna T. Malladi, Hongzhong Zheng
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Patent number: 11775296Abstract: The present disclosure includes apparatuses and methods related to mask patterns generated in memory from seed vectors. An example method includes performing operations on a plurality of data units of a seed vector and generating, by performance of the operations, a vector element in a mask pattern.Type: GrantFiled: April 12, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventor: Jeremiah J. Willcock
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Patent number: 11768689Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: GrantFiled: November 12, 2021Date of Patent: September 26, 2023Assignee: Movidius LimitedInventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
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Patent number: 11768690Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.Type: GrantFiled: November 22, 2021Date of Patent: September 26, 2023Assignee: Apple Inc.Inventors: Aditya Kesiraju, Andrew J. Beaumont-Smith, Brian P. Lilly, James Vash, Jason M. Kassoff, Krishna C. Potnuru, Rajdeep L. Bhuyar, Ran A. Chachick, Tyler J. Huberty, Derek R. Kumar
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Patent number: 11748108Abstract: Example embodiments of the present application provide an instruction executing method and apparatus, an electronic device, and a computer-readable storage medium that may be applied in the field of artificial intelligence. The instruction executing method may include: executing an instruction sequence that includes memory instructions and non-memory instructions, the instructions in the sequence executed starting to be executed in order; determining that execution of a first memory instruction needs to be completed before a second memory instruction starts to be executed, the second memory instruction being a next memory instruction following the first memory instruction in the instruction sequence; and executing non-memory instructions between the first memory instruction and the second memory instruction without executing the second memory instruction, during a cycle of executing the first memory instruction.Type: GrantFiled: March 24, 2021Date of Patent: September 5, 2023Assignees: Beijing Baidu Netcom Science and Technology Co., LTD., Kunlunxin Technology (Beijing) Company LimitedInventors: Yingnan Xu, Jian Ouyang, Xueliang Du, Kang An
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Patent number: 11748104Abstract: Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.Type: GrantFiled: July 29, 2020Date of Patent: September 5, 2023Assignee: International Business Machines CorporationInventors: Bryan Lloyd, David A. Hrusecky, Sundeep Chadha, Dung Q. Nguyen, Christian Gerhard Zoellin, Brian W. Thompto, Sheldon Bernard Levenstein, Phillip G. Williams
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Patent number: 11740900Abstract: Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.Type: GrantFiled: June 22, 2021Date of Patent: August 29, 2023Assignee: Marvell Asia Pte LtdInventor: Lawrence Said
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Patent number: 11734007Abstract: A system parses a very long instruction word (VLIW) to obtain an execution parameter. The system obtains a first sliding window width count, a first sliding window height count, a first feature map width count, and a first feature map height count that correspond to first target data. In accordance with a determination that the first sliding window width count falls within the sliding window width range, the first sliding window height count falls within the sliding window height range, (the first feature map width count falls within the feature map width range, and the first feature map height count falls within the feature map height range, the system determines an offset of the first target data. The system also obtains a starting address of the first target data, and adds the starting address to the offset to obtain a first target address of the first target data.Type: GrantFiled: April 26, 2022Date of Patent: August 22, 2023Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Xiaoyu Yu, Dewei Chen, Heng Zhang, Yan Xiong, Jianlin Gao
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Patent number: 11734224Abstract: Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.Type: GrantFiled: September 28, 2020Date of Patent: August 22, 2023Assignee: Tenstorrent Inc.Inventors: Ivan Matosevic, Davor Capalija, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin, Djordje Maksimovic, Ljubisa Bajic
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Patent number: 11734016Abstract: A method for parallel processing of a data stream is provided. In the method, a data stream that includes a plurality of segments is received. A split operation is performed on the data stream based on a split buffer to split the plurality of segments into N sub-streams. Each of the N sub-streams includes one or more segments of the plurality of segments, the N being a positive integer. The split buffer includes an input indexed first in first out (iFIFO) buffer, the input iFIFO buffer being configured to receive the plurality of segments of the data stream and output the plurality of segments to N sub-input iFIFO buffers to generate the N sub-streams. N sub-processing tasks are performed on the N sub-streams to generate N processed sub-streams.Type: GrantFiled: June 30, 2022Date of Patent: August 22, 2023Assignee: Tencent America LLCInventor: Iraj Sodagar