Patents Examined by William Kraig
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Patent number: 8940637Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: GrantFiled: July 5, 2012Date of Patent: January 27, 2015Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
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Patent number: 8940617Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: November 21, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Patent number: 8941089Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.Type: GrantFiled: February 14, 2013Date of Patent: January 27, 2015Assignee: Adesto Technologies CorporationInventors: Chakravarthy Gopalan, Jeffrey Shields, Venkatesh Gopinath, Janet Siao-Yian Wang, Kuei-Chang Tsai
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Patent number: 7372086Abstract: A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the semiconductor substrate and an insulator provided in the trench, a part of the isolation region in the trench around the MOSFET having a bottom deeper than other part of the isolation region.Type: GrantFiled: April 8, 2004Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Sato, Ichiro Mizushima
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Patent number: 7339192Abstract: An active-matrix substrate 30 includes multiple function lines 31, a structure for fixing up the arrangement of the function lines, a first conductive layer 43, a second conductive layer 42, multiple transistors 32 and multiple pixel electrodes 33. Each of the function lines 31 includes: a core 36, at least the surface of which has electrical conductivity; an insulating layer 37 that covers the surface of the core; and a semiconductor layer 38 that covers the insulating layer. Some portions of the first and second conductive layers 43 and 42 overlap with the respective semiconductor layers of the function lines but the others not. The transistors 32 are provided so as to have their channel defined as a region 44 in the semiconductor layer by the first and second conductive layers. The pixel electrodes 33 are electrically connected to the first conductive layer 43.Type: GrantFiled: November 8, 2002Date of Patent: March 4, 2008Assignee: Sharp Kabushiki KaishaInventors: Hirohiko Nishiki, Osamu Sakai, Akitsugu Hatano
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Patent number: 7326979Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.Type: GrantFiled: September 19, 2003Date of Patent: February 5, 2008Inventors: Darrell Rinerson, Wayne Kinney, John E. Sanchez, Jr., Steven W. Longcor, Steve Kuo-Ren Hsia, Edmond Ward, Christophe Chevallier
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Patent number: 7268409Abstract: A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least one of the plurality of active devices is located within a columnar region having a cross-sectional shape substantially conforming to a perimeter of the inductor. The at least one of the plurality of active devices may be biased based on a desired Q factor of the inductor or and/or an operating frequency of the microelectronic device.Type: GrantFiled: May 21, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Min Tseng, Chih-Sheng Chang
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Patent number: 7262484Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.Type: GrantFiled: May 9, 2005Date of Patent: August 28, 2007Assignee: International Business Machines CorporationInventors: James S. Dunn, David L. Harame, Jeffrey B. Johnson, Alvin J. Joseph
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Patent number: 7242057Abstract: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.Type: GrantFiled: August 26, 2004Date of Patent: July 10, 2007Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Grant S. Huglin
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Patent number: 7196349Abstract: Multi-quantum well (MQW) spatial light modulator devices are disclosed that are capable of achieving reasonable quantum efficiencies and high contrast ratios in order to close an optical communication link by resolving the logical on or off state. The device both modulates and detects light through the use of the quantum well design and resonant cavity enhancement. Based on the materials (e.g., InGaAs/InAlAs) and their band structures, this device can be configured to communicate in the eye-safe wavelength range (e.g., 1550±20 nm). The device can be fabricated using standard photolithographic processes such as molecular beam epitaxy (MBE) and inductively coupled plasma (ICP) reactive ion etching (RIE).Type: GrantFiled: February 17, 2005Date of Patent: March 27, 2007Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Kambiz Alavi, Joseph Pellegrino, Patrick G Maloney, F. Elliott Koch
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Patent number: 7148522Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.Type: GrantFiled: December 11, 2004Date of Patent: December 12, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai, Weining Li
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Patent number: 7091527Abstract: A semiconductor photodetection device includes a semiconductor structure including an optical absorption layer having a photo-incidence surface on a first side thereof, a dielectric reflecting layer formed on a second side of the semiconductor structure opposite to the first side, a contact electrode surrounding the dielectric reflecting layer and contacting with the semiconductor structure, and a close contact electrode covering the dielectric reflecting layer and contacting with the contact electrode and the dielectric reflecting layer, wherein the close contact electrode adheres to the dielectric reflecting layer more strongly than to the contact electrode.Type: GrantFiled: June 27, 2005Date of Patent: August 15, 2006Assignee: Fujitsu Quantum Devices LimitedInventors: Yoshihiro Yoneda, Ikuo Hanawa
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Patent number: 7087477Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.Type: GrantFiled: November 12, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: David M. Fried, Randy W. Mann, K. Paul Muller, Edward J. Nowak
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Patent number: 7045863Abstract: An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain silicide film is not provided in a portion located on a boundary of each transistor and divided to correspond to the respective transistors. As a result, regions between respective pairs of the transistors have high resistances, and it is, therefore, possible to prevent a current from flowing between the different transistors and prevent local current concentration. It is thereby possible to allow the electrostatic discharge protected transistor to make most use of an electrostatic destruction protection capability per unit area without increasing an area of the transistor.Type: GrantFiled: January 5, 2005Date of Patent: May 16, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiro Kogami, Katsuhiro Ootani, Katsuya Arai