Abstract: A method of fabricating a complex IC in two parts and making the electrical connections between them afterwards is described. By this method, a ferroelectric RAM is fabricated in two parts, where the first part has an array of unit cells each of those has a transistor or a group of transistors serving the purpose of selecting one address for data recording and has an array of electrically conductive pads facing upward, protruding out from the surface of the first part, where the second part consists of a data-recording layer on another substrate. The data-recording layer consists of ferroelectric material and is pressed on the first part during data writing and reading.

Abstract: A semiconductor device includes a transistor mounted on the top surface of a substrate. A metal sheet is disposed on a metallized electrode on the substrate to which the emitter, for example, of the transistor is electrically connected. The emitter is electrically connected by a thin metal wire to the metal sheet. An MOS capacitor is disposed on the metal sheet, and a plated through-hole beneath the metal sheet connects the metallized electrode directly to a metallized ground electrode disposed on the bottom surface of the substrate.

Abstract: The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array.