Patents Examined by William Silverio
  • Patent number: 6015955
    Abstract: A device and method for enabling the reworkability of an integrated circuit. The device includes a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: January 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mukta Shaji Farooq, Raymond Alan Jackson, Sudipta Kumar Ray
  • Patent number: 5986217
    Abstract: A printed circuit board for minimizing thermally-induced mechanical damage of solder joints electrically connecting electronic components to the printed circuit board. The printed circuit board includes a first substrate, solder pads, and an expansion layer. The first substrate has two substantially parallel major surfaces, and a first coefficient of thermal expansion (CTE). The solder pads are located on one of the major surfaces of the substrate. The expansion layer has a second CTE, different than the first CTE, and is affixed to a portion of one of the major surfaces. The expansion layer is also arranged to provide a predetermined degree of bending for a given temperature change to a portion of the first substrate proximate to the expansion layer and to two of the solder pads, thus forming a concavity in the portion of the substrate.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: November 16, 1999
    Assignee: Hewlett-Packard Company
    Inventor: Michael J. Strum
  • Patent number: 5981873
    Abstract: A printed circuit board for a BGA semiconductor package provided at one corner thereof with a degating opening serving as a mold runner gate during a process of molding a resin seal adapted to protect the semiconductor chip and serving as a region for degating a surplus resin formed after the molding process and a method for molding a BGA semiconductor using the printed circuit board. The degating opening has an inverted triangular shape having curved lateral sides and a vertex, at which the lateral sides join together, disposed in a region for forming the resin seal, or an inverted trapezoidal shape having one end disposed in the resin seal region.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: November 9, 1999
    Assignees: Anam Semiconductor Inc., Amkor Technology, Inc.
    Inventor: Young Wook Heo
  • Patent number: 5973262
    Abstract: There is provided a distribution apparatus in which transmission losses at the connections between ends of transmission lines and input and output terminals of a mother board are reduced. These ends of the transmission lines are positioned on resin support pieces. A resin support piece (19) is provided at a dead end of each groove (6a) formed in a housing (1). An end portion of a metal rod (6b) is placed on the support piece (19). The end portion of the rod (6b) has a threaded hole (20) formed therethrough. The mother board (11) is provided with two first lands (22,23) each surrounding a screw hole (21). A screw (22a) is tightened in each threaded hole (20), which is part of a main line connection terminal (5b), thereby bringing the head of the screw (22a) into firm contact with the first land (22) and establishing an electrical connection between the first land (22) and the conductive rod (6b).
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: October 26, 1999
    Assignee: Maspro Denkoh Co., Ltd.
    Inventor: Hiroshi Matubara
  • Patent number: 5965848
    Abstract: A disposable portable electronic device has a body of prescribed length and thickness and constructed of an elongate, ribbon-like substrate of dielectric material, the substrate having a continuous length much greater than the length of the body, and a thickness much less than the thickness of the body, with conductors and components formed on the substrate, the dielectric material of the substrate having a high degree of flexibility such that the substrate is folded upon itself into at least shorter lengths juxtaposed with one another within the thickness of the body, and the juxtaposed lengths of the substrate are secured together to establish a self-sustaining structure which forms the body of the device.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: October 12, 1999
    Assignee: Randice-Lisa Altschul
    Inventors: Randice-Lisa Altschul, Lee S. Volpe
  • Patent number: 5949029
    Abstract: Several different types of electrically conductive elastomers are disclosed along with the methods for their fabrication. In one particular embodiment, a layered composition is disclosed which comprises a substrate, a first layer, and a second layer. The substrate is formed of a non-conductive elastic material and it has an outer surface. The first layer, which is formed with a non-conductive elastic material, is grafted to the outer surface of the substrate. The second layer, which is formed with a non-conductive elastic material having a quantity of conductive flakes interspersed therein, is grafted to an outer surface of the first layer. The second layer can further be formed with a quantity of rounded or jagged conductive particles interspersed in the non-conductive elastic material such that some of the conductive particles are present along an outer surface of the second layer. Alternatively, a quantity of rounded or jagged conductive particles may be imbedded in an outer surface of the second layer.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: September 7, 1999
    Assignee: Thomas & Betts International, Inc.
    Inventors: David R. Crotzer, Jonathan W. Goodwin, Arthur G. Michaud, David A. DeDonato
  • Patent number: 5943598
    Abstract: A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a first polysilicon layer overlying and in contact with the semiconductor substrate. Second, a plurality of conductive structures are patterned from the first polysilicon layer. Third, there is formed a dielectric layer having an upper planar surface and having a lower surface contacting the semiconductor substrate and the plurality of conductive structures from the first polysilicon layer. Fourth, there is formed a second polysilicon layer overlying and in contact with the dielectric layer. Fifth, a plurality of conductive structures are formed from the second polysilicon layer. Lastly, there is formed a metallic layer over the plurality of conductive structures from the second polysilicon layer.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: August 24, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Yih-Shung Lin
  • Patent number: 5920037
    Abstract: The present invention provides a new device and technique for enhancing the electrical properties of the thick metal backer/adhesive bond/ground plane interface. The enhanced electrical properties are obtained by micro-roughening a connection surface of the thick metal backer prior to forming the thick metal backer/adhesive bond/ground plane interface.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: July 6, 1999
    Assignee: International Business Machines Corporation
    Inventors: Lisa Jeanine Jimarez, David Noel Light, Andrew Michael Seman, David Brian Stone
  • Patent number: 5917157
    Abstract: A strongly adherent laminate with enhanced thermal conductivity and high dielectric strength. The preferred embodiment includes an aluminum-surfaced substrate, a copper layer adjacent the aluminum oxide layer, and optionally, a tin/silver layer adjacent the copper deposition layer, forming a base substrate laminate for mounting a multilayer wiring board laminate to has been discovered. Another embodiment includes a metallic-surfaced substrate, an adjacent vapor-deposited dielectric layer, a metallic conductor layer adjacent the dielectric layer, and optionally, a solder layer adjacent the metallic conductor layer. Surprisingly, such construction has been demonstrated to have a self-healing dielectric whereby dielectric breakdown strength is maintained in repeated tests. Such laminates will find utility in the electronics industry in the fabrication of printed circuit boards and afford a combination of high adhesion, thermal conductivity, and dielectric strength heretofore unknown in the industry.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: June 29, 1999
    Inventor: Ralph Remsburg
  • Patent number: 5912438
    Abstract: In a method of assembling an electronic component onto a substrate, a fiducial is defined by a solder mask positioned upon the substrate. A fiducial-defining window in the mask has a base of the window completely provided with a material of different light-reflecting quality than the mask surface. This provides for the peripheral edge of the window, i.e. the mask, to be the edge of the fiducial. Windows in the mask which expose terminal pads upon the substrate and fixed in position relative to edges of the fiducial and both these windows and the fiducial are determined by the mask. Surface mount components are then located upon the substrate relative to the window positions and not relative to the terminal pad positions. This process reduces the number of incorrect connections of terminals of components to terminal pads.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: June 15, 1999
    Assignee: Northern Telecom Limited
    Inventor: Richard Kubin
  • Patent number: 5910641
    Abstract: An electrically conductive adhesive film having a pattern of microscopic elongate metal particles which extend from one surface to the other to provide an interconnection between confronting conductive metal pads abutting the surface. The particles have sharp ends to penetrate the oxide coating on the conductive metal pads of an electronic module when force is applied to press the module against the film.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: June 8, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Jaynal A. Molla
  • Patent number: 5910644
    Abstract: A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating of nickel; an intermediate layer of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating of soft gold. The intermediate layer may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale). The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: June 8, 1999
    Assignee: International Business Machines Corporation
    Inventors: Dale E. Goodman, Mark K. Hoffmeyer, Roger S. Krabbenhoft
  • Patent number: 5909010
    Abstract: A CSP (Chip Size Package) of the present invention includes a semiconductor IC (Integrated Circuit) chip having I/O (Input/Output) terminals along its edges. A small size substrate has a smaller contour than the chip and has a plurality of metal terminals arranged along the edges of its bottom, and a plurality of metal bumps arranged on its top in a lattice configuration. The top of the chip and the bottom of the substrate are so configured as to be electrically connected to each other via a tape member including a plurality of leads. These leads each include a first terminal to be electrically connected to the associated I/O terminal of the chip, and a second terminal to be electrically connected to the associated metal terminal of the substrate.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: June 1, 1999
    Assignee: NEC Corporation
    Inventor: Tatsuo Inoue
  • Patent number: 5909009
    Abstract: A laminate organic resin wiring board and a method of producing the same are disclosed. The wiring board has a plurality of subassemblies each having a conductive resin layer serving as a ground or feed layer on its top. The subassemblies are adhered to each other at their conductive resin layers. This successfully eliminates the need for an organic resin layer for insulation customarily formed on the top of the individual subassembly. The decrease in the number of layers reduces the period of time necessary for the production of the wiring board.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: June 1, 1999
    Assignee: NEC Corporation
    Inventor: Shinji Tanaka
  • Patent number: 5892179
    Abstract: A solder bump structure on a microelectronic substrate including an electrical contact having an exposed portion. This solder bump structure includes an under bump metallurgy structure on the microelectronic substrate, and a solder structure on the under bump metallurgy structure opposite the microelectronic substrate. The metallurgy structure includes an elongate portion having a first end which electronically contacts the exposed portion of the electrical contact and an enlarged width portion connected to a second end of the elongate portion. The solder structure includes an elongate portion on the metallurgy structure and an enlarged width portion on the enlarged width portion of the metallurgy structure. Accordingly, the enlarged width portion of the solder structure can be formed on a portion of the microelectronic substrate other than the contact pad and still be electronically connected to the pad.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: April 6, 1999
    Assignee: MCNC
    Inventors: Glenn A. Rinne, Joseph Daniel Mis
  • Patent number: 5883335
    Abstract: An electrical connection structure for electrically connecting a chip on a mounting surface of a printed circuit board to a back surface of the printed circuit board includes a printed circuit board having a mounting surface and a back surface, the mounting and back surfaces being opposite surfaces of the printed circuit board, a through hole through the printed circuit board and extending from the mounting to the back surface, an electrical conductive layer between the mounting and back surfaces and a layer that permits wiring over the through hole that is electrically isolated from the electrical conductive layer.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: March 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mizumoto, Yutaka Tsukada