Abstract: A vector scan operation is performed to generate M data elements of a result vector, where each result data element corresponds to a combination of an additional data element S with at least some of the data elements of a source vector operand V. The vector scan operation is performed using a plurality of steps, each step comprising one or more combination operations for combining data elements. At least one of the steps includes two or more combination operations performed in parallel. At least two of the steps comprise a combination operation for combining a data element with the additional data element S. This approach enables the vector scan operation to be performed in fewer steps in the case where fewer than M data elements are active, so that the vector scan operation can be performed more quickly.

Abstract: An apparatus for mapping an architectural register to a physical register can include a memory and control circuitry. The memory can be configured to store an intra-core register rename map and an inter-core register rename map. The intra-core register rename map can be configured to map the architectural register to the physical register of a core of a multi-core processor. The inter-core register rename map can be configured to relate the architectural register to an identification of the first core in response to determining that the physical register is a location of a most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core, the most recent write according to program order. The control circuitry can be configured to maintain the intra-core register rename map and the inter-core register rename map.