Abstract: A light-emitting element includes a light-emitting layer, an upper electrode provided on a first side of the light-emitting layer, and a lower electrode provided on a second side of the light-emitting layer opposite to the first side. The lower electrode is constituted by a first electrode and a second electrode including a first gap therebetween, the second electrode having an area larger than that of the first electrode. The upper electrode is constituted by a third electrode and a fourth electrode including a second gap therebetween, the third electrode facing the first electrode and the second electrode, the fourth electrode facing the second electrode and having an area smaller than that of the third electrode.

Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Abstract: A modified double magnetic tunnel junction (mDMTJ) structure is provided which includes a narrow base and the use of a spin diffusion layer (i.e., non-magnetic, spin-conducting metallic layer) which gives a low resistance-area product (RA) for the tunnel barrier layer that forms an interface with the spin diffusion layer.

Abstract: The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.

Abstract: An electronic component includes a substrate; a stack of two layers of different semiconductor materials, designed to form a layer of electron gas at the interface thereof or close to same; and a buried barrier forming a separation between the substrate and said stack. The buried barrier includes a first layer of a ternary alloy of semiconductor material of the III-N type, having an increasing concentration of one of the chemical species of the ternary alloy of the first layer the closer it is to the substrate; and a second layer of a ternary alloy of semiconductor material of the III-N type, formed beneath the first layer and having a decreasing concentration of one of the chemical species of the ternary alloy of the first layer the closer it is to the substrate.

Abstract: A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

Abstract: A method for fabricating a semiconductor device includes forming a source structure over a lower structure with interconnections; forming a first contact plug that penetrates the source structure to be coupled to the interconnections, and a first sacrificial pad that penetrates the source structure and is spaced apart from the first contact plug; forming an upper structure that covers the first sacrificial pad, the first contact plug, and the source structure; forming a second contact plug that penetrates the upper structure and contacts the first contact plug, forming a second sacrificial pad that penetrates the upper structure to contact the first sacrificial pad and is spaced apart from the second contact plug; and replacing the first sacrificial pad and the second sacrificial pad with a dielectric supporter.

Abstract: A display device includes: a first substrate including a display area to emit a light having a peak wavelength from light emitting areas and a non-display area surrounding the display area; and a second substrate including transparent areas overlapping the light emitting areas and to convert the peak wavelength of the light or to transmit the light through the transparent areas. The second substrate includes: a base layer including the transparent areas, an inner light blocking area arranged between the transparent areas, and an outer light blocking area arranged outside the transparent areas; a color filter on the base layer; and a light blocking layer above the color filter and including an outer light blocking layer overlapping the outer light blocking area and an inner light blocking layer overlapping the inner light blocking area.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.

Abstract: An image sensor includes a first structure including a first substrate, and a first internal wiring structure on the first substrate. The first substrate includes an active pixel region and a through electrode region around the active pixel region. The first internal wiring structure includes a plurality of first internal wiring patterns. The image sensor further includes a second structure including a second substrate and a second internal wiring structure on the second substrate. The second substrate is arranged on the first substrate. The image sensor additionally includes a through electrode layer arranged in the through electrode region to at least partially fill a through electrode trench, which penetrates the first substrate, and to connect the first internal wiring structure to the second internal wiring structure.

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.

Abstract: A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.

Abstract: An approach to provide a funnel-shaped spin-transfer torque (STT) magnetoresistive random-access memory (MRAM) device with a dual magnetic tunnel junction. The approach includes providing a metal pillar on a connection to a semiconductor device. The approach includes providing a first reference layer on the metal pillar and on a portion of a first interlayer dielectric adjacent to the metal pillar. The approach includes providing a first tunnel barrier on the first reference layer and a free layer on the first tunnel barrier layer. The approach includes providing a second tunnel barrier on the free layer and a second reference layer on the second tunnel barrier of the semiconductor structure of the funnel-shaped spin-transfer torque MRAM device.

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

Abstract: A semiconductor storage device includes: a substrate; a stacked body; a columnar body; and a single-crystalline body. The stacked body includes a cell array region where first insulating layers and conductive layers are alternately stacked. The columnar body has a first columnar body. The first columnar body includes a semiconductor body and a charge accumulation film provided between one of a plurality of the conductive layers and the semiconductor body, and is present in the cell array region. The conductive layer that surrounds an outer periphery of the single-crystalline body and that is closest to the substrate among the conductive layers is a first layer, and that the conductive layer that surrounds an outer periphery of the first columnar body and that is closest to the substrate among the conductive layers is a second layer.

Abstract: An image sensor includes a substrate having a first surface and a second surface that are opposite to each other. The substrate including a plurality of unit pixel regions having photoelectric conversion regions and floating diffusion regions disposed adjacent to the first surface. A pixel isolation pattern is disposed in the substrate and is configured to define the plurality of unit pixel regions. An interconnection layer is disposed on the first surface of the substrate. The interconnection layer includes a conductive structure having a connection portion that extends parallel to the first surface of the substrate and is spaced apart from the first surface of the substrate. Contacts extend vertically from the connection portion towards the first surface of the substrate. Each of the contacts are spaced apart from each other with the pixel isolation pattern interposed therebetween. The contacts are coupled to the floating diffusion regions, respectively.

Abstract: A semiconductor chip includes: an epitaxial film made of gallium nitride; a semiconductor element disposed in the epitaxial film; a chip formation substrate including the epitaxial film and having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface; and a convex and a concavity on the side surface.

Abstract: A method for porosifying a Ill-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first Ill-nitride material, having a charge carrier density greater than 5×1017 cm?3, beneath a surface layer of a second Ill-nitride material, having a charge carrier density of between 1×1014 cm?3 and 1×1017 cm?3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first Ill-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.