Patents Examined by Woo M. Choi
  • Patent number: 6779078
    Abstract: A method of selecting logical volumes that are the targets for data migration to equilibrate the load on a system, based on the accessing data of the physical drives and logical drives under the disk array controllers, without increasing the load of the disk array controller. An external manager communicates with two or more disk array controllers, gathers and manages the access data and the configuration data relating to the physical drives and logical volumes of each disk array controller, and prepares an optimum data migration instruction to equilibrate the access load.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: August 17, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Akira Murotani, Toshio Nakano, Akinobu Shimada
  • Patent number: 6718453
    Abstract: A method and apparatus for non-contiguous translation protection table that includes one or more first registers, two or more second registers, an address translator, and a detector. Each first register contains a value denoting a size of each of two or more blocks of memory. Each second register contains a value denoting the starting physical address of an associated one of the two or more blocks of memory. The address translator receives a virtual address and translates the virtual address to a physical address of one of the two or more blocks of memory. The detector detects whether the received virtual address is outside of the range of the two or more blocks of memory. The blocks of memory may be translation protection tables that reside in physically non-contiguous memory locations.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Brian M. Collins, Dick Reohr