Abstract: The invention provides a PCI bridge chip for communicating command data between a primary PCI bus and a secondary PCI bus. A primary command transaction logic manages command data transfers from the primary PCI bus to the secondary PCI bus. The primary delayed transaction logic has a plurality of primary buffers for buffering command transactions to be issued on the secondary PCI bus selectively. A secondary command transaction logic manages command data transfers from the secondary PCI bus to the primary PCI bus. The second delayed transaction logic has a plurality of secondary buffers for buffering command transactions to be issued on the primary PCI bus selectively. The primary and secondary command transaction logic can for example include three buffers to buffer transaction commands in the appropriate direction. The bridge chip further provides for coupling large burst data through a memory section and to external an external RAM (or alternatively internal memory).