Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.

Abstract: A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.

Abstract: A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

Abstract: A display module is provided including a pixel region having a plurality of pixels and a black matrix arranged outside the pixel region. Each of the pixels is separated from adjacent pixels by a first interval, a left distance from the left edge to a first one of the plurality of pixels plus a right distance from a second one of the plurality of pixels to the right edge is a first distance, and a bottom distance from the bottom edge to a third one of the plurality of pixels plus a top distance from a fourth one of the plurality of pixels to the top edge is the first distance.

Abstract: Interconnect structures and methods for forming an interconnect structure. A sacrificial layer is formed on a substrate and an interconnect opening is formed that extends vertically through the sacrificial layer into the substrate. The interconnect opening is filled with a conductor to form a conductive feature. After filling the interconnect opening with the conductor, a dielectric layer is formed on the sacrificial layer. After the dielectric layer is formed on the sacrificial layer, the sacrificial layer is removed to form an air gap layer arranged vertically between the dielectric layer and the substrate.

Abstract: A display device includes a substrate having an edge portion, a display region located on the substrate and separated from the edge portion, a drive circuit region between the display region and the edge portion, a terminal region on the edge portion; and wirings in the display region, the drive circuit region, and an area between the drive circuit region and the terminal region, wherein at least one wiring of the wirings include a first conductive layer, a second conductive layer overlapping the first conductive layer in a plan view and separated from the first conductive layer, a first connection portion where the first conductive layer and the second conductive layer are electrically connected, a second connection portion where the first conductive layer and the second conductive layer are electrically connected, and the first connection portion is separated from the second connection portion.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.

Abstract: A display unit includes: a drive wire; a planarization layer covering the drive wire and having a connection hole; a relay electrode provided on the planarization layer and configured to be electrically connected to the drive wire through the connection hole; a filling member made of an insulating material and provided in the connection hole; a first partition wall made of a same material as that of the filling member and covering an end of the relay electrode; a first electrode covering the filling member and configured to be electrically connected to the relay electrode; a second electrode facing the first electrode; and a functional layer located between the first electrode and the second electrode, the functional layer including a light-emitting layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Abstract: A light emitting diode includes: an n-type nitride semiconductor layer; an active layer over the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer over the active layer. The n-type nitride semiconductor layer includes: an n-type nitride layer; a first intermediate layer over the n-type nitride layer; an n-type modulation-doped layer over the first intermediate layer. The light emitting diodes includes a second intermediate layer over the n-type modulation-doped layer. The second intermediate layer includes a sub-layer having a higher n-type doping concentration that an n-type doping concentration of the n-type modulation-doped layer.

Abstract: An optoelectronic component (100) comprises an optoelectronic semiconductor chip (10), a first contact area (31) and a second contact area (32), which is laterally offset with respect to the first contact area and is electrically insulated therefrom, and a housing element (40). The first contact area (31) is electrically conductively connected to the first semiconductor layer (21) and the second contact area (32) is electrically conductively connected to the second semiconductor layer (22) of the optoelectronic semiconductor chip. The first contact area (31) and the second contact area (32) project beyond the optoelectronic semiconductor chip laterally in each case. The housing element (40) is fixed to the first contact area (31) and the second contact area (32) in regions in which the first contact area (31) and the second contact area (32) project beyond the optoelectronic semiconductor chip laterally in each case. The housing element surrounds the optoelectronic semiconductor chip at least partly.

Abstract: A light guide grid can include a grid structure having a plurality of intersecting grid lines, each grid line having a width w, and a plurality of openings for photosensor elements between intersecting grid lines. The grid structure has a diagonal grid width between two adjacent ones of the plurality of openings in a diagonal direction. The diagonal grid width has a value exceeding approximately ?3 w. An image sensor can include a light guide grid having a grid structure as described above and further include a micro-lens such as a sinking micro-lens and a color filter. A method of fabricating a light guide grid can include forming a grid above at least one photo sensor, the grid having intersecting grid lines of width w and a diagonal grid width in a diagonal direction having a value exceeding approximately ?3 w.

Abstract: Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise Si, SiC, or other materials. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices.

Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. The silicon transistors may be configured in a top gate arrangement. The oxide transistors may be configured in a top gate or a bottom gate arrangement. In one embodiment, source-drain contacts for the silicon and oxide transistors may be formed simultaneously. In another embodiment, the silicon and oxide thin-film transistor structures may be formed using at least three metal routing layers.

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a first nanosheet channel layer, a second nanosheet channel layer, and first, second, and third sacrificial layers that are vertically arranged between the first and second nanosheet channel layers. The first, second, and third sacrificial layers are laterally recessed relative to the first and second nanosheet channel layers to form a cavity indented into a sidewall of the first body feature. The second sacrificial layer is laterally recessed to a lesser extent than the first sacrificial layer or the third sacrificial layer such that an end of the second sacrificial layer projects into the cavity between the first and third sacrificial layers. A dielectric spacer is formed in the first and second portions of cavity between the first and second nanosheet channel layers.

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.