Abstract: A method and apparatus for sharing a logic block between multiple peripheral/input/output I/O devices. A method and apparatus for generating a first interrupt in response to a request from one of the devices. A second interrupt is also generated. The second interrupt is recognized before the first interrupt, such that the second interrupt is handled first and causes the logic block to be configured for the requested device. Then the first interrupt is then handled in which the request to the desired device is serviced using the reconfigured hardware.

Abstract: A design and engineering project management system comprising a computer including a microprocessor, program memory, data storage memory, one or more displays, logic for identifying overall product objectives and group objectives relating to each of one or more subsystems or components of the overall product and displaying the overall objective and group objectives in a plurality of graphic windows which are quickly retrieved by the system operator, thereby integrating the diverse interests and activities of the groups into a comprehensive system design and implementation program. The system also preferably includes logic for identifying one or more strategies for achieving group objectives and presenting the strategies in a graphic form which allows for quick comparison of competing strategies.

Abstract: A medical image processing apparatus includes a color video monitor (image displaying device) 3 and an arithmetic and control circuit 4. When the apparatus is supplied with electric power and begins to operate, the arithmetic and control circuit 4 causes a color density bar 32 and a color density bar 42 to be displayed in parallel on a display screen 3a l of the color video monitor 3. The color density bars 32, 42 each serve as a display adjusting image. The color density bar 32 is formed such that a density gradually becomes deep from an end of the bar 32 to the other end of the same. In the color density bar 42, it is deepened in a direction opposite to that of the color density bar 32.

Abstract: A system and method for monitoring and verifying inventory. The system comprises a portable computer with a printer and modem all "cabled" together and maintained in a carrying case. The portable computer communicates with a mainframe computer on which certain dealer inventory information is maintained. Software, residing on a disk which is accessible by the portable computer, allows for the input of dealer codes which are used to identify inventory information which is downloaded from the mainframe computer to the portable computer. The inventory information is used to support an audit of a dealer's inventory. The system of the present invention provides an auditor with an up-to-date record a dealer's current inventory. The system also provides the auditor with a device for printing out a checklist for use in undertaking the inventory, for preparing reconciliation reports for verifying the auditor's findings with the dealer and an input for inputting the results of the inventory.

Abstract: A diverse goods arbitration system and method allocates computer resources among bidding requesters. Bid slates are transmitted to an arbiter by users (requesters) requesting use of specified portions of the available computer resources. Each bid slate may contain a plurality of bids, each bid representing a requested set of resources and a bid price. The arbiter selects combinations of bids from the bid slates, where each bid combination consists of no more than one bid from each of the received bid slates. The arbiter rejects all bid combinations whose constituent bids exceed an established maximum allocation level for any computer resource. It then selects as a winning bid combination the bid combination having the highest total bid price. Computer resources are then allocated for a next time period based on the winning bid. Costs are allocating to each successful requester in accordance with a predefined opportunity cost function.

Abstract: A buffer is acquired from a buffer storage area when the system is started up. The buffer allocated to a program requiring a use of a buffer is monitored so that a reallocation is performed when the buffer count becomes smaller than a predetermined threshold value.

Abstract: The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56 and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. The bus repeater/switch (40) includes a plurality of bus interface cards (48) that are connected to the distributed arbitration buses (52, 54, 56 and 58) for receiving signals from and transmitting signals to devices (62, 64, 66, 68, 72 and 74) connected thereto. The bus interface cards (48) connect to a control card (44) which allows signals from one of the sharing buses (52, 54 or 56) to be exchanged with the shared bus (58). The bus switch (40) also includes selector switch (84 or 88) for choosing which particular one of the sharing buses (52, 54 or 56) exchanges digital data signals with the shared bus (58).

Abstract: A system for interfacing an optical disk autochanger having a robot and a plurality of disk drives to a host includes a master SCSI bus, a subordinate SCSI bus, a SCSI multiplexer and a move controller. The master SCSI bus is connected to the host. The subordinate SCSI bus is connected to the plurality of disk drives. The multiplexer is connected between the master SCSI bus and the subordinate SCSI bus. The multiplexer transfers communications between the host and a selected disk drive. The move controller receives jukebox control commands from the host and selects the disk drive based on the jukebox control commands.

Abstract: A cache SRAM connector assembly comprising a connector, a number of latches, and a number of high performance switches, is provided to a computer system. The connector removably connects either asynchronous or burst cache SRAM to a processor bus. The latches store cache access addresses being driven on a number of address lines of the processor bus. The high performance switches being coupled to both the latches and the address lines of the processor bus selectively provide the cache SRAM with latched access addresses as required by asynchronous cache SRAM or directly driven access addresses on the processor bus as required by burst cache SRAM.

Abstract: Apparatus for providing shared access to a shared RAM in situations where the shared RAM is electrically connected to a relatively slow address/data bus, and shared access is desired from a relatively faster address bus and data bus. An address buffer is connected between the address bus and the address/data bus, the address buffer for selectably buffering address information between those buses under control of an address buffer selection signal. A data buffer is connected between the data bus and the address/data bus, the data buffer for selectably buffering data information between those buses under control of a data buffer selection signal. A gate array is connected to the address/data bus, the gate array controlling access the shared RAM. A logic array is connected to the address bus and is responsive to address information on the address bus which corresponds to addresses of the shared RAM.

Abstract: The present invention, generally speaking, provides a system and method of decoupling the address and data buses of a system bus using side band information signals. A computer system with which the invention may be used has a system bus including an address bus and a data bus and has, operatively connected to said system bus, multiple master devices, including a microprocessor, and multiple slave devices. In accordance with one embodiment of the invention, the address bus and the data bus are decoupled by providing, in addition to signals carried by the system bus, first side-band signals including, for each master device besides the microprocessor, an address arbitration signal, and providing, in addition to signals carried by the system bus, second side-band signals including, for each slave device, an address termination signal, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus.

Abstract: A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on the bus, and a bus controller that limits the types of transactions that can be sent on the bus at any given time. When one module is performing an atomic operation, the bus controller limits transactions to those that do not change the memory image that existed when the atomic operation was commenced. The bus controller, however, permits responses or returns of data, assuming the response or return does not alter the current value of data.

Abstract: A computer system includes a chipset which controls the gate-A20 signal and the CPU RESET signal in a conventional manner in response to commands from a system microprocessor. The computer system further includes a peripheral controller which is programmed to generate an alternative gate-A20 signal and an alternative CPU RESET signal when the peripheral controller has been commanded to override the corresponding signals from the chipset. Two signal selectors controlled by the peripheral controller select either the gate-A20 signal and the CPU RESET signal from the chipset or the alternative gate-A20 signal and the alternative CPU RESET signal from the peripheral controller as respective outputs to control operations of the computer system. The use of the alternative signals permits certain operations of the computer systems to be directly controlled by an application program without being intercepted by the operating system.

Abstract: A bus-based apparatus and method for synchronous priority arbitration between modules in a computer system. The modules in the system have priority codes selected from the set D(r,K+1) of r-digit radix K+1 numbers. Each stage in the arbitration method includes the steps of writing to a bus, performing a prefix-OR operation on the bus, and reading from the bus. Arbitration is completed in, at most, r units of time. The design of the system can be optimized for speed, logic per module, and/or the number of modules connected to any bus line. Both arbitration time and arbitration logic may be decreased by increasing the bus width. The number of modules can be increased indefinitely by increasing only bus-width, while keeping arbitration time and arbitration logic fixed. The arbitration bus is a wired-OR bus.

Abstract: An improved method for correcting spelling errors in text wherein candidate expressions for replacing a misspelled word are assigned probability functions. The misspelled word can be replaced automatically with the candidate expression having the highest probability function or candidate expressions can be displayed to a user in rank order of their probability functions for the user to make a choice. The probability function for a candidate expression is based on (1) the probability of occurrence of the candidate expression appearing in text and/or (2) the probability of occurrence of the particular typographical modification needed to convert the candidate expression into the misspelled word.

Abstract: A voltage discharge circuit discharges the voltage across a charge storage device, such as a capacitor, at an output of a power supply. The discharge circuit may be used, for example, in a contrast power supply for an LCD panel. The discharge circuit uses one or more switches to control the coupling between the output capacitor and a discharge element, such as a resistor. When the power supply is enabled, the discharge resistor is not coupled to the output capacitor, so that the discharge circuit does not significantly affect the operation of the power supply. When the power supply is disabled, the switches couple the discharge resistor to the output capacitor to discharge any accumulated voltage at a relatively fast rate. For a contrast power supply for an LCD display, a switching power supply is preferred.

Abstract: In an X-ray computerized tomography apparatus, a water phantom is interposed between an X-ray tube unit and an X-ray detector in place of a subject under examination and a plurality of pieces of data detected by a plurality of X-ray detector elements are previously measured as a pieces of compensation data while shifting the X-focal point to different positions. Compensation data corresponding to the actual position of the X-ray focal point, which shifts according to the thermal state of the X-ray tube unit, is selected to correct detect data obtained for a subject under examination, permitting optimum compensation of variations in sensitivity among the X-ray detector elements for any position of the X-ray focal point, thereby preventing a ring-like artifact from being produced on a tomography image.

Abstract: An interprocessor interrupt hardware unit ("IIU") for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor sets up a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU retrieves a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and reads the registers to obtain the control block. The host processor clears the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed.

Abstract: In a processor having a central processing unit, an instruction cache and a data cache, a bus controller is provided for controlling giving and receiving of a signal between internal instruction and data buses and external bus. Upon concurrent miss of instruction cache and data cache, the bus controller executes an external instruction access with priority in case where the external instruction access is a same page access as a previous external DRAM access, and executes an external data access in the other cases. Thereby, the cycle number required for the external access is reduced, while reducing the number of instruction execution cycles as a total.

Abstract: An interface between unsynchronised devices such as ASICs. The interface comprises a delay means which synchronises the write strobe of the first device with the system clock of the second device, thus enabling the transfer of data from the first device to the second device. The interface requires fewer gates per register in the second device than prior art interfaces.