Abstract: A method for relative pin placement guidance, comprising the steps of (A) placing a plurality of pins to form a pinout in response to a first design, a second design and an attribute and (B) determining one or more placement constraints, one or more groups of the pins, and routing of the pins in response to the attribute.
Abstract: A method for determining a wiring pattern of a signal line for connection of a circuit on a multi-layer printed wiring board includes the steps of providing a constraint of an electrical length which the signal line must satisfy, determining an electrical length change at a discontinuous delay part of the signal line along which a signal propagates, determining a wiring route of the signal line, calculating an electrical length of the signal line with use of a wiring length of the signal line and the determined electrical length change, judging whether or not the calculated electrical length satisfies the electrical length constraint given to the signal line, and determining the wiring route as a wiring pattern when the electrical length constraint is satisfied as the decision result, thereby carrying out a wiring layout to make an electrical length constraint satisfied.
Abstract: A method of determining a desired connection path between a pair of points of a net separated by one or more blockages, while reducing path delays and ramp time violations and without placing buffers within any of the blockages.
Type:
Grant
Filed:
March 6, 2002
Date of Patent:
September 2, 2003
Assignee:
LSI Logic Corporation
Inventors:
Elyar E. Gasanov, Valery B. Kudryavtsev, Andrey A. Nikitin