Abstract: The present invention introduces several methods for implementing non Manhattan routing systems for integrated circuit manufacture. In one embodiment, a non Manhattan routing system is implemented by memorizing where intersections between wiring pitch grids occur and connecting such intersections with vias. In another embodiment, a gridless non Manhattan routing systems may be implemented by adapting a gridless Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: Method and apparatus for recognizing data path structures in a netlist. The stages in the netlist are identified. Each stage includes a set of components that process multiple bits. The buses that connect the stages are also identified. A graph is generated to represent the stages and buses. The vertices in the graph represent the stages and the edges represent the buses. The graph is divided into subgraphs having terminating vertices that represent memory elements. Each subgraph represents a data path structure.

Abstract: A machine-learning model may be created to perform integrated circuit layout extraction. Using such a machine-learning system has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system performs machine learning using Bayesian inference in order to train the neural network models. The Bayesian inference may be implemented with normal Monte Carlo techniques, Hybrid Monte Carlo techniques, or other Bayesian learning techniques. After the creation of a set of models for each of the smaller simpler extraction problems, the machine-learning based models may be used for extraction.

Abstract: The present invention includes a table-driven system for guiding a user through the design of an electronic component. The system utilizes data tables that are adapted to house data relating an electronic component. A modular program is used to extract data from these tables. The modular program contains system logic to utilize this data in guiding the user through the process. A terminal is then used to allow a user to make selections from the choices prompted by the modular program and complete the design process.

Abstract: An electronic system with a plurality of components interconnected by a plurality of shared communication channels. At least one component comprises a communication architecture tuner. The tuner enables the electronic system to adapt to changing communication needs of the electronic system.

Abstract: Methods and apparatuses for fully defining static random access memory (SRAM) using phase shifting layouts are described. The approach includes identifying that a layout includes SRAM cells and defining phase shifting regions in a mask description to fully define the SRAM cells. The phase conflicts between adjacent phase shifters are resolved by selecting cutting patterns designed for the SRAM shape and functional structure. Additionally, the transistor gates of the SRAM cells can be reduced in size relative to the original SRAM layout design. Thus, an SRAM cell can be lithographically printed with small, consistent critical dimensions including extremely small gate lengths resulting in higher yields and improved performance.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

Abstract: The problem of searching for a low cost path from a source location to a target location through a traversable region partitioned into a plurality of tiles is solved using source and target cost functions. Each tile in the traversable region is defined by boundary segments. The source cost function provides a cost for traversing from the source location to the boundary segment in question. The target cost function provides a cost for traversing from the boundary segment in question to the target location. The target cost function is estimated, and the source cost function is calculated. A path cost function is determined by adding the source and target cost functions. If the target location is a tile, then the target cost may be estimated using a convex hull of the target tile and the boundary segment in question. To facilitate the cost function calculations, multiple forms of cost function propagation between segments are disclosed.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: An improved ASIC design support system is described. In accordance with the ASIC design support system, it is possible to easily download the latest versions of a necessary library (or libraries) and a necessary simulator. The ASIC design support system includes a web server which receives a request of the customer including the specification of the ASIC he wants to design. The web server serves to generate and transfer to the customer a library (or libraries) or a simulator required for designing said ASIC and performing simulation thereof.

Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.

Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: A method and apparatus for a driver layout is described. The layout includes an first number of gate lines arranged along a first axis and a second equal number of gates arranged along a second axis, such that the first set of gates lines is orthogonal to the second set of gates lines. The layout includes a total of N discrete transistors.