Abstract: A conventional initial deep trench structure consists of a patterned Si3N4 pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO2 collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO2 is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO2 is etched at least 6 times faster than the Si3N4 (stopping on the Si3N4 pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6× the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages.

Abstract: A process for DRAM cell production includes (1) depositing a layer of a first substance in a trench; (2) depositing a first layer of a second substance in said trench; (3) growing an interfacial layer of oxide between said layer of said first substance and said first layer of said second substance, and between side walls of said trench and said first layer of said second substance; (4) applying an anisotropic etching substance to the surface of said first layer of said second substance, thereby exposing said interfacial layer of oxide; (5) applying a second etching substance to the surface of said first layer of said second substance thereby substantially removing said interfacial layer of oxide; and (6) depositing a second layer of said second substance in said trench. The process reduces the contact resistance of the buried strap and improves the production yield for low temperature performance cells.

Abstract: Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

Abstract: A method for making a thin dielectric layer is disclosed which is useful in fabricating semiconductor devices, particularly transistors and DRAM cell devices. The method comprises a two-steps, i.e., (i) growing a base layer of dielectric material on a substrate having a thickness in excess of the desired thickness for the layer, and (ii) etching back the base layer to the desired thickness. With these two steps, a thin dielectric layer of less than 20 Å may be provided having substantial uniformity across its surface with a standard deviation in surface contours of less than 0.7 Å.

Abstract: A method and structure for forming an integrated circuit chip having at least one opening in a substrate includes forming an opening having vertical walls in the substrate, protecting a first portion of the vertical walls of the opening, leaving a second portion of the vertical walls unprotected, and laterally patterning the second portion of the opening to change a shape or property of the opening.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Abstract: Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed on the substrate. A layer of a conductive material, such as polysilicon, is formed on the gate oxide layer, masked and etched to form an extended-width gate having endcaps of a greater width than the endcap design rules. A second mask is formed to cover the extended-width gate up to the desired width of the endcaps (i.e., the design width) and to expose the portions of the extended-width gate beyond the endcap design width. The exposed portions of the extended-width gate are then etched, resulting in a completed gate having endcaps of the design width. Since the endcaps are initially formed to a greater width than the design width, any pullback that occurs during printing of the mask or etching of the gate does not cause the gate to be insufficiently wide to avoid source/drain leakage.

Abstract: A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.

Abstract: A system for performing chemical mechanical polishing wherein a dopant is added to the slurry during a chemical mechanical planarization so as to enhance end point determination. In one embodiment the CMP system includes a laser end point detection system that provides a signal indicative of the intensity of light being reflected off of the surface that is being removed by CMP. The slurry that is used in the CMP process is doped with a surfactant such that false peaks in intensity of the reflected signal is reduced so that the end point intensity peak resulting from the laser reflecting off of an underlying surface is more definite.

Abstract: Acoustic wave devices are fabricated and packaged together while in wafer form. The devices are formed as dies on a first wafer, which may be quartz crystal. A second wafer, e.g., of alumina or another ceramic, has vias formed in it at positions that correspond to the locations of metallic bus bars on the first wafer, and a grid of an anisotropic conductive thermoplastic material is applied onto the second wafer. The two wafers are laminated, and treated with pressure and heat. The anisotropic conductive material seals the dies, and also connects the die bus bars through the vias to outside conductors. A thin passivation layer, e.g., SiO2, may provide hermetic sealing of the sensitive areas of the die. The devices may be tested robotically in wafer form before singulation.

Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.

Abstract: In a semiconductor device, a pair of diffusion regions are placed in a silicon substrate. Herein, the diffusion regions serve as source and drain regions. Further, a gate oxide film is formed between the diffusion layers or regions and on the silicon substrate. Moreover, a gate electrode is placed on the gate oxide film. In addition, a diamond-like carbon layer is formed over the silicon substrate so as to cover at least the gate oxide film. With such a structure, the diamond-like carbon layer prevents water from diffusing into the gate oxide film.

Abstract: A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced.

Abstract: A method for preventing the cluster defect of HSG is disclosed. Where the cluster defect means that when wafer with HSGs are cleaned just when HSGs are formed, there are a plurality of clusters appear on HSGs. In comparison with conventional fabrication that wafer and HSGs are directly cleaned just when these HSGs are formed. The idea behind the invention is that when HSGs are formed, a heat treatment is applied to change surface states of HSGs before wafer and HSGs are cleaned. Owing to the fact that these surface states of HSGs are improved by the heat treatment, no cluster will be formed during following clean process. Thus, the formation of cluster is obviously protected and then quality of any application of HSGs is improved by the invention.

Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.

Abstract: A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

Abstract: A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract: A method of forming a capacitor of a semiconductor device which can prevent disconnection between lower electrodes by blanket-depositing a second conductive film for silicidation on a semiconductor substrate and forming an oxide of the second conductive film such as titanium dioxide (TiO2) on an interlayer dielectric using high temperature oxidation, before depositing a dielectric film, and which can obtain a high capacitance by forming both a silicide layer including the second conductive film, and the oxide of the second conductive film such as titanium dioxide (TiO2) having a high dielectric constant, on a lower electrode, and using the silicide layer and oxide as the dielectric film.

Abstract: A fabrication method for an ultra short channel device comprising a self-aligned landing pad is described in which a first opening is formed in the oxide layer to define a gate structure region. A pad oxide layer is then formed in the first opening covering the substrate followed by forming a spacer on the inner sidewall of the first opening. Using the spacer as an etching mask, a portion of the oxide layer is removed to form a second opening exposing the substrate. A gate oxide layer is then deposited in the second opening, followed by forming a first conductive layer to fill the second opening. A third opening is then formed in the oxide layer to expose the substrate and to define the source/drain region. An ion implantation is then conducted in the substrate of the third opening to form a heavily doped region of the source/drain region. Thereafter, a landing pad is formed to fill the third opening and to electrically connect with the source/drain region.