Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.

Abstract: A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

Abstract: A system to configure a conductive pathway and a method of forming a system of configurable conductivity pathways include a photosensitive layer that becomes conductive based on photoexcitation, and a light source layer deposited over the photosensitive layer, the light source layer selectively providing the photoexcitation to the photosensitive layer. The system further includes a controller to control the light source layer, the controller illuminating a portion of the light source layer corresponding with a user input image to photoexcite the photosensitive layer and configure the conductive pathway in the photosensitive layer according to the image.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.

Abstract: A thin film transistor array substrate includes a substrate, a plurality of pixel elements arranged on the substrate, each of the pixel elements including a thin film transistor and a pixel electrode electrically connected with the thin film transistor, a light shielding electrode disposed between the substrate and the thin film transistor to shield a channel of the thin film transistor, and a storage capacitor including a first electrode and a second electrode disposed opposite to each other. The light shielding electrode includes a transparent electrically-conductive layer and a non-transparent electrically-conductive layer stacked on top of each other. The first electrode of the storage capacitor is disposed in a same layer and of a same material as the transparent electrically-conductive layer of the light shielding electrode.

Abstract: Embodiments of the invention provide an array substrate and a fabrication method thereof and a display device. The fabrication method of an array substrate includes: forming a semiconductor active layer, a gate insulating layer and a gate electrode on a substrate; forming a light-shielding layer; forming a first color filter layer, forming a second color filter layer and forming a third color filter layer; and forming via holes that respectively penetrate through the first color filter layer, the second color filter layer and the third color filter layers; and forming a pixel electrode and source and drain electrodes.

Abstract: In at least one embodiment of the method, the method is used to produce optoelectronic semiconductor components. A lead frame assemblage includes a plurality of lead frames. The lead frames each includes at least two lead frame parts and the lead frames in the lead frame assemblage are electrically connected to one another by connecting webs. The lead frame assemblage is fitted on an intermediate carrier. At least a portion of the connecting webs is removed and/or interrupted. Additional electrical connecting elements are fitted between adjacent lead frames and/or lead frame parts. A potting body mechanically connects the lead frame parts of the individual lead frames to one another. The resulting structure is singulated to form the semiconductor components.

Abstract: The invention relates to a method for producing a plurality of optoelectronic components, comprising the following steps: —providing an auxiliary support wafer (1) having contact structures (4), wherein the auxiliary support wafer comprises glass, sapphire, or a semiconductor material, —applying a plurality of radiation-emitting semiconductor bodies (5) to the contact structures (4), —encapsulating an least the contact structures (4) with a potting mass (10), and —removing the auxiliary support wafer (1). The invention further relates to an optoelectronic component.

Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.

Abstract: A system to configure a conductive pathway and a method of forming a system of configurable conductivity pathways are described. The system includes a photosensitive layer that becomes conductive based on photoexcitation, and a light source layer deposited over the photosensitive layer, the light source layer selectively providing the photoexcitation to the photosensitive layer. The system further includes a controller to control the light source layer, the controller illuminating a portion of the light source layer corresponding with a user input image to photoexcite the photosentive layer and configure the conductive pathway in the photosensitive layer according to the image.

Abstract: Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.

Abstract: A TFT substrate and a method of manufacturing the TFT array substrate are disclosed. The method includes providing a substrate, forming an organic layer on the substrate, forming a first transparent conductive layer on the organic layer, and forming a photolithography layer on the first transparent conductive layer, where the photolithography layer has an opening. The method also includes patterning the first transparent conductive layer to form a first via hole in the first transparent layer using the photolithography layer as a mask, where the first via hole is aligned with the opening in the photolithography layer, and patterning the organic layer to form a second via hole in the organic using the photolithography layer as a mask, where the second via hole is aligned with the opening in the photolithography layer.

Abstract: A semiconductor structure includes a resistor on a substrate formed substantially simultaneously with other device elements, such as one or more transistors. A diffusion barrier layer deposited on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor in a substantially similar manner as that used to form the gate of the transistor. The filler material is removed.

Abstract: A semiconductor device includes a semiconductor element having a semiconductor chip and connection terminals, a cooling fin to which the semiconductor element is fixed, and an external cooling body having a passage for cooling medium, the cooling fin being fixed to the external cooling body. The semiconductor element has a protruding cooling block that is inserted and fixed to the cooling fin, which in turn is fixed to the external cooling body such that the cooling fin is in contact with the cooling medium.

Abstract: To provide a novel resistor. To provide a display device having a novel structure that can improve its reliability. To provide a display device having a novel structure that can reduce electrostatic discharge damages. The resistor includes a semiconductor layer and an insulating layer formed over the semiconductor layer, and the semiconductor layer is an oxide represented by an In-M-Zn oxide that contains at least indium (In), zinc (Zn), and M (M is a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and the insulating layer contains at least hydrogen.

Abstract: A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.

Abstract: A thin film transistor, comprising: a substrate; a first electrode formed on the substrate; a first insulation layer formed on the first electrode; a gate electrode formed on the first insulation layer; a second insulation layer formed on the gate electrode; an active layer penetrating through the first and second insulation layers and electrically isolated from the gate electrode; and a second electrode formed on the active layer and electrically connected to the first electrode through the active layer, wherein the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode.

Abstract: A power module, having a printed circuit board core, which contains at least one electronic power component embedded in an insulating layer, the core being arranged between two heat dissipation plates, wherein each heat dissipation plate has a metal outer layer and a metal inner layer electrically separated from said metal outer layer by a thermally conductive, electrically insulating intermediate layer, and electrode terminals of the at least one power component are guided out from the core via terminal lines, wherein the printed circuit board core on both sides of the insulating layer has a conductor layer, at least one conductor layer is structured at least in portions, and each conductor layer is connected at least in portions via a conductive, metal intermediate layer to a metal inner layer of the heat dissipation plate, contacts run from the structured conductor layer to the electrode terminals of the at least one power component, and at least one power terminal of the at least one power component is co

Abstract: A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor.