Abstract: A vertical floating gate transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a floating gate electrode in a trench that extends vertically through those regions and a control or programming gate electrode above and separated from the floating gate electrode. A process for forming the vertical floating gate transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and the floating and control gates. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry.

Abstract: The present invention develops a process for forming dual conductive wells in a silicon substrate for an integrated circuit by: forming an oxide layer on the silicon substrate; patterning an oxidation barrier layer on the oxide layer, thereby defining active areas for active devices; introducing first p-type conductive impurities into the silicon substrate thereby forming at least one p-type conductively doped well region; masking over the p-type conductively doped well region; introducing n-type conductive impurities into the silicon substrate thereby forming at least one n-type conductively doped well region; removing the masking; forming oxide regions in areas not covered by the patterned oxidation barrier layer; and forcing the p-type and n-type conductive impurities further into the silicon substrate thereby forming the dual well regions, the well regions having adequate conductive depth to provide for the formation of the active devices.