Abstract: A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

Abstract: A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. The processing engines can be arranged in pipelines, with different processing engines executing different steps in a sequence of operations. Flow control or data synchronization between pipeline stages can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management. Firmware instructions can define data flow by reference to a virtual address space associated with pipeline buffers. A hardware interlock controller within the pipeline can track and enforce the data dependencies for the pipeline.

Abstract: A device includes protocol logic to determine a packet type for a packet and generate and send the corresponding packet. The packet includes a packet header with a header base, the header base including a type field and a header content field. The type field indicates the packet type and the header content field indicates which of a plurality of header content blocks is to be included in the packet header with the header base. Information in fields of the header base indicate a total length of the packet.

Abstract: The invention provides a technology for suppressing a delay in communication between a plurality of cores that perform parallel processing. In the invention, an ECU 302 of a vehicle control system 2 includes a plurality of cores 401 and a shared memory 405. When transmitting data in the inter-core communication, a transmission side core 401-1 writes a counter value updated according to the data and a writing order to a buffer unit 901 which is determined by a counter value managed for each communication system, which is stored in each of the plurality of buffer units 901 provided in the shared memory 405. When receiving data in the inter-core communication, a reception side core 401-2 reads data from the buffer unit 901 in which the latest data for each communication system is stored, which is determined by the counter value stored in each of the plurality of buffer units 901.

Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.

Abstract: A high-energy-efficiency binary neural network accelerator applicable to artificial intelligence Internet of Things is provided. 0.3-0.6V sub/near threshold 10T1C multiplication bit units with series capacitors are configured for charge domain binary convolution. An anti-process deviation differential voltage amplification array between bit lines and DACs is configured for robust pre-amplification in 0.3V batch standardized operations. A lazy bit line reset scheme further reduces energy, and inference accuracy losses can be ignored. Therefore, a binary neural network accelerator chip based on in-memory computation achieves peak energy efficiency of 18.5 POPS/W and 6.06 POPS/W, which are respectively improved by 21× and 135× compared with previous macro and system work [9, 11].

Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

Abstract: Embodiments are provided for centralized control of execution of a quantum program. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a synchronization component that causes multiple controller devices remotely located relative to the system to be synchronized with one another and the system. The computer-executable components also include an ingestion component that accesses measurement data resulting from one or more measurements at respective qubit devices. The computer-executable components further include a composition component that generates, using the measurement data, one or more control messages for respective second controller devices of the multiple controller devices.

Abstract: A system including a computer storage and a processor is described. The computer storage is configured to identify a stored data as protected. The processor is configured to perform speculative execution. To perform the speculative execution, the processor is configured to determine, in response to the speculative execution of an instruction to read the stored data, whether the stored data is identified as protected. In response to a determination that the stored data attempted to be read during the speculative execution is protected, the processor is configured to disallow during the speculative execution immediate successful completion of the instruction to read the stored data.

Abstract: In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

Abstract: A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to control the interface and to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.

Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

Abstract: An apparatus and method for efficient microcode patching.

Abstract: Devices and techniques for pipeline merging in a circuit are described herein. A parallel pipeline result can be obtained for a transaction index of a parallel pipeline. Here, the parallel pipeline is one of several parallel pipelines that share transaction indices. An element in a vector can be marked. The element corresponds to the transaction index. The vector is one of several vectors respectively assigned to the several parallel pipelines. Further each element in the several vectors corresponds to a possible transaction index with respective elements between vectors corresponding to the same transaction index. Elements between the several vectors that correspond to the same transaction index can be compared to determine when a transaction is complete. In response to the transaction being complete, the result can be released to an output buffer in response to the transaction being complete.

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

Abstract: Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Abstract: Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.