Abstract: An image sensor includes a pixel array and a logic circuit. The pixel array includes a pixel isolation layer between a plurality of pixels. Each of the plurality of pixels include a pixel circuit below at least one photodiode. The logic circuit acquires a pixel signal from the plurality of pixels. The pixel array includes at least one autofocusing pixel, which includes a first photodiode, a second photodiode, a pixel internal isolation layer between the first and second photodiodes, and a microlens on the first and second photodiodes. The pixel internal isolation layer includes a first pixel internal isolation layer and a second pixel internal isolation layer, separated from each other in a first direction, perpendicular to the upper surface of the substrate, and the first pixel internal isolation layer and the second pixel internal isolation layer include different materials.

Abstract: A color control member includes a color control layer including a quantum dot and a color filter layer on the color control layer, wherein a low refractive layer may be between the color control layer and the color filter layer. The low refractive layer includes a base resin and a plurality of sets of hollow particles dispersed in the base resin, and each of the hollow particles of each set of the sets of hollow particles may have a spherical shape. The sets of hollow particles may have respective average diameters, and a ratio of two average diameters of the respective average diameters of the sets of hollow particles is about 2:1 to about 60:1, and the low refractive layer including the hollow particles may be formed through a continuous process at a low temperature.

Abstract: The present disclosure relates to a display substrate, a display panel and a display device. The display substrate includes: a base substrate including a display area and a peripheral area surrounding the display area; a common electrode located in the peripheral area and surrounding the display area; a panel crack detection line located in the peripheral area and surrounding the display area, wherein the panel crack detection line is located on one side of the common electrode away from the display area; and at least one electrostatic discharge circuit located in the peripheral area, wherein the at least one electrostatic discharge circuit includes at least one first thin film transistor including an active layer, a gate, a source and a drain, the source and the drain are electrically connected to the panel crack detection line, and the gate is electrically connected to the common electrode.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, and at least one memory structure. The first conductive layer includes a first portion, a second portion, and a third portion, a fourth portion, and a fifth portion. The first portion is provided between the second portion and the third portion in a second direction. The second conductive layer includes a sixth portion, a seventh portion, and an eighth portion, a ninth portion, and a tenth portion. The sixth portion is provided between the seventh portion and the eighth portion in the second direction. The second portion is provided between the sixth portion and the eighth portion in the second direction.

Abstract: A semiconductor device fabrication method in which a growing process is followed by a capping process in which a phosphor containing material cap layer is deposited over a final GaAs based layer. The wafer, containing many such substrates, can be removed from the reaction chamber to continue processing at a later time without creating an oxide layer on the final GaAs based layer. In continuing processing, a decomposition process selectively decomposes the phosphor containing material cap layer, after which a regrowing process is performed to grow additional layers of the device structure. The capping, decomposition and regrowth processes can be repeated multiple times on the semiconductor devices on the wafer during device fabrication.

Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: A semiconductor storage device includes: a substrate layer; and a stacked body that is provided on the substrate layer. The semiconductor storage device includes a columnar portion that includes a semiconductor body extending within the stacked body in a stacking direction. The semiconductor storage device includes: an insulating layer provided on the plurality of terrace portions; and a plurality of columnar bodies extending in a first direction and provided within the insulating layer. The semiconductor storage device includes slit portions that split the stacked body into a plurality of string units. Each of the columnar bodies adjacent to each of the slit portions has a core film, the semiconductor body, a tunnel insulating film, and a block insulating film formed in sequence from a shaft center side to an outer periphery side of the columnar body, and the columnar body does not have the charge storage portion.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.