Abstract: A data processing system may include at least two memory systems including first and second memory systems to which a logical address and a command are applied in parallel from a host.

Abstract: In general, techniques are described for logical defragmenting of a storage device. A controller of a storage device groups sequential logical block addresses of a logical span into a plurality of groups. Each group includes a same number of logical block addresses, and each logical block address references a physical location of a physical block on the storage device. For each group, the controller determines whether at least one logical block address references a physical location of a physical block that includes valid data. Responsive to the at least one logical block address referencing valid data, the controller stores a first value to a field of a bit-level indirection table. The bit-level indirection table includes a number of fields equal to a number of groups of sequential logical block addresses. Responsive none of the logical block addresses referencing valid data, the controller stores a second value to the field.

Abstract: Described are techniques for updating checkpoint data during a copy process that copies data from a first device to a second device. A portion of data is copied from the first device to the second device. A first calculated value is determined in accordance with a plurality of factors. In accordance with the first calculated value and a threshold ratio, it is determined whether to update the checkpoint data denoting progress of the copying process that copies data from the first device to the second device. If it is determined to update the checkpoint data, first processing is performed that updates the checkpoint data.

Abstract: A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers.

Abstract: Mechanisms for concurrent update of data in cache with destage of data from the cache to disk by a processor device. A second copy of the data is established in the cache and on a cache directory. A first copy of the data and the second copy of the data are adjacently ordered in the cache directory. One of the first and second copies is held for an update operation so as to include a latest data modification, while the remaining copy concurrently is used for a destage operation to disk.

Abstract: A first-in-first-out (FIFO) memory device may include a plurality of memory locations configurable into M input queues comprising sequences of input data values and N output queues for storing sequences of output data values, wherein N is not equal to M.

Abstract: Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. A centralized Memory Management logic Unit (MMU) is located in the interconnect for virtualization and sharing of integrated circuit resources including target cores between the one or more initiator IP cores. A master translation look aside buffer (TLB) stores virtualization and sharing information in the entries of the master TLB. A set of two or more translation look aside buffers (TLBs) locally store virtualization and sharing information replicated from the master TLB. Logic in the MMU or other software updates the virtualization and sharing information replicated from the master TLB in the entries of one or more of the set of local TLBs.

Abstract: Embodiments of the present invention provide an approach for intelligent storage planning and planning within a clustered computing environment (e.g., a cloud computing environment). Specifically, embodiments of the present invention will first determine/identify a set of storage area network volume controllers (SVCs) that is accessible from a host that has submitted a request for access to storage. Thereafter, a set of managed disk (mdisk) groups (i.e., corresponding to the set of SVCs) that are candidates for satisfying the request will be determined. This set of mdisk groups will then be filtered based on available space therein, a set of user/requester preferences, and optionally, a set of performance characteristics. Then, a particular mdisk group will be selected from the set of mdisk groups based on the filtering.

Abstract: A cache management method using checkpoint tags in checkpoint mode includes steps of: receiving a request to save data; fetching at least one cache block including the data from cache memory; writing the data from the at least one cache block into the data array; writing a physical address and metadata of the cache block into an array of cache memory tags; and upon receipt of a restore request: fetching an identifier for the at least one cache block stored in the checkpoint tag array; reloading the cache memory with the at least one cache block in the checkpoint tag array; and switching to normal mode.

Abstract: A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the data array; a checkpoint tag array storing data identification information; and a cache controller with prefetch logic.

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.

Abstract: Proposed are a storage apparatus and hierarchical data management method for promoting the effective usage of memory apparatuses while suppressing maintenance-related costs and work. The storage apparatus comprises a plurality of memory apparatuses of a plurality of types, and a control unit for executing required data migration by monitoring an access frequency to each of the unit areas of the virtual volume and by controlling the corresponding memory apparatuses so that the storage area provided by the memory apparatus with a superior response performance is allocated to unit areas for which the access frequency is higher.

Abstract: A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.

Abstract: Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.

Abstract: A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration that allows a flashcopy (FC) map to be started when a target disk is already the source of an active FC map.

Abstract: There is provided an apparatus for controlling a flash memory, which includes a memory for storing a plurality of flash translation layers; and a control block for, when an access is requested from outside, determining a pattern of the access, selecting one of the flash translation layers stored in the memory based on the determination result, and managing mapping data of the flash memory based on the selected flash translation layer.

Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

Abstract: A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.