Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the the machine configuration.

Abstract: A memory device includes memory groups, storing data, and a boosting interface. The boosting interface transfers the data by determining a transfer path of the data based on a command and an access address. The boosting interface includes a reconfigurable input decoder in which a program command of the command is programmed based on a command set mode and an input-output set mode. The memory device has an enhanced performance by programming the program command in the reconfigurable input decoder based on the command set mode and the input-output set mode.

Abstract: Disclosed is an improved approach to implement memory-efficient cache size estimations. A HyperLogLog is used to efficiently approximate an MRC with sufficient granularity to size caches.

Abstract: A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

Abstract: A storage module may be configured to perform log storage operations on a storage log maintained on a non-volatile storage medium. An I/O client may utilize storage services of the storage module to maintain an upper-level log. The storage module may be configured to coordinate log storage and/or management operations between the storage log and the upper-level log. The coordination may include adapting a segment size of the logs to reduce write amplification. The coordination may further include coordinating validity information between log layers, adapting log grooming operations to reduce storage recovery overhead, defragmenting upper-level log data within the storage address space, preventing fragmentation of upper-level log data, and so on. The storage module may coordinate log operations by use of log coordination messages communicated between log layers.

Abstract: A file access method and apparatus, and a storage device are presented, where the file access method is applied to a storage device in which a file system is established based on a memory. The storage device obtains, according to a file identifier of a to-be-accessed first target file, an index node of the first target file in metadata, where the index node of the first target file stores information about first virtual space of the first target file in global virtual space. The storage device maps the first virtual space onto second virtual space of a process, and performs addressing on an added file management register to access the first target file according to a start address of the first virtual space and a base address of a page directory of the global file page table stored in the file management register.

Abstract: Threads using hardware transactions and executing instrumented critical sections that do not perform any writes may complete as long as the thread holding the lock has not yet executed its first write operation. If the thread executing the instrumented critical section performs any writes, or if the thread holding the lock performs any writes during its critical section, the hardware transaction may be aborted. A write flag may be used to determine whether the thread holding the lock performs any writes. The thread holding the lock may set the flag before performing any write operation. The thread executing the hardware transaction may subscribe to that flag and abort the transaction if the flag is set to true, indicating that the thread holding the lock performed a write operation.

Abstract: Embodiments relate to a virtualized storage environment with one or more virtual machines operating on a host and sharing host resources. Each virtual machine has a virtual disk in communication with a persistent storage device. The virtual machine(s) may be misaligned with the persistent storage device so that a virtual block address does not correspond with a persistent storage block address. A relationship between the virtual disk(s) and the persistent storage device is established, and more specifically, an alignment delta between the devices is established. The delta is employed to translate the virtual address to the persistent address so that the virtual and persistent storage blocks are aligned to satisfy a read or write operation.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

Abstract: A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.

Abstract: Methods of sudden power off recovery may include reading dirty-block meta-pages from memory blocks on a dirty block list, recording mapping in formation in open-block meta-pages, serving host commands by looking up logical block addresses (LBAs) in the dirty-block meta-pages and the open-block meta-pages and when an LBA is not found in the dirty-block meta-pages and the open-block meta-pages, reading new mapping information from a dirty table and saving the new mapping information in host-write meta-pages.

Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.

Abstract: A method for restoring a data volume using incremental snapshots of the data volume includes creating a first series of incremental snapshots according to a first predefined interval. The method further includes creating a second series of incremental snapshots according to a second predefined interval that is an integer multiple of the first predefined interval. The method also includes receiving a request to restore the data volume to a point-in-time. The method further includes restoring the data volume to the point-in-time using none or some of the snapshots in the first series that were created at or prior to the point-in-time, and all of the snapshots in the second series that were created at or prior to the point-in-time.

Abstract: Presented herein are methods, non-transitory computer readable media, and devices for integrating a workload management scheme for a file system buffer cache with a global recycle queue infrastructure.

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract: An operating method of a data storage device includes setting a first page access unit using a first page electrically coupled with a first word line of a first plane and a second page electrically coupled with a second word line of a second plane; and setting a second page access unit using a third page electrically coupled with a second word line of the first plane and a fourth page electrically coupled with a first word line of the second plane.

Abstract: A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections; memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections; and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate modified data for storage within the memory circuits in response to at least one command received on the interface; wherein the at least one command is supplemental to read and write commands executable by the memory device.