Abstract: A memory power control command may be received from a host and may include either a first power control command or a second power control command. The first power control command may correspond to the host not using a memory device, and the second power control command may correspond to the host using the memory device. It may be determined whether to activate a memory processor based on the memory power control command and on memory processor activation information. When the memory processor is activated based on the determining, an operation of the memory processor may be started based on the first power control command or ended based on the second power control command. When the memory processor is inactivated based on the determining, it may be determined whether to activate or inactivate the memory based on the memory power control command.

Abstract: An appliance is described. A write engine may process a write request from an application to write a first data into a memory. The write request may including the first data and an address. A compression engine may compress the first data to produce a first compressed data. A write module may store the first compressed data in the memory. The first data may be a first part of a page that may further include a second data as a second part. The first compressed data may be a first part of a compressed page that may further include a second compressed data as a second part.

Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for data access. The method includes acquiring a priority of a workload associated with an input/output (I/O) instruction of a user, and determining, based on the priority, whether to perform data access to a persistent memory indicated by the I/O instruction by using a central processing unit (CPU). If it is determined not to perform the data access by using the CPU, the data access is performed by using a programmable data moving apparatus. The method according to the embodiments of the present disclosure can avoid that important workloads compete for CPU resources equally with secondary workloads, and alleviate blocking of workloads due to insufficient CPU resources, thereby improving the overall performance of persistent memory access.

Abstract: Methods, systems, and devices for memory system logical unit number (LUN) procedures are described. A memory system may receive an indication to convert a LUN for storing LBAs associated with an application from a first type to a second type, where the second type is associated with a higher performance defragmentation process than the first type. The memory system may perform defragmentation on data associated with the LUN based on converting the LUN to the second type. The memory system may determine whether the LBAs stored in the LUN are ordered based on the defragmentation, and the memory system may operate (e.g., execute) the application based on the LBAs being ordered.

Abstract: A sparse data storage method for deep learning, a computer device and a storage medium. The method includes: obtaining an offset between current non-zero data and previous non-zero data of the current non-zero data, and generating to-be-transmitted data according to the current non-zero data and the offset, where the to-be-transmitted data is stored in a first memory; obtaining the to-be-transmitted data, calculating an address increment according to the offset, and obtaining, according to the address increment, a storage address in which the current non-zero data is to be stored in a second memory; and transmitting the current non-zero data to the second memory, and storing the current non-zero data in the storage address in the second memory. According to the embodiments, the power consumption and costs required by deep learning operations can be reduced.

Abstract: An inflight-I/O-based storage emulation system includes a storage emulation device coupled to host devices, and to storage devices that provide primary, secondary, and metadata storage systems. The storage emulation device stores I/O commands directed to the primary storage system by the host devices in its I/O queue. If the storage emulation device predicts I/O operations for I/O commands in its I/O queue do not exceed a threshold, it executes at least some of those I/O commands to store first data in the primary storage system. If the storage emulation device predicts I/O operations for I/O commands in its I/O queue exceed the threshold, it executes at least some of those I/O commands to store second data in the secondary storage system, and provides mapping information in the metadata storage system that identifies storage location(s) in the primary storage system associated with the second data in the secondary storage system.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data. An SSD controller may manage reading and writing data to the flash memory. The SSD may include an automatic stream detection logic to select a stream identifier responsive to attributes of data. A garbage collection logic may select an erase block and program valid data in the erase block into a second block responsive to a stream ID determined the automatic stream detection logic. The stream ID may be determined after the garbage collection logic has selected the erase block for garbage collection.

Abstract: One example method includes performing delta operations to protect data. During a delta operation, a primary map and a secondary map are processed using bit logic. The bit logic determines how to handle data stored at a location on the volume associated with an entry in the primary map and included in the current delta operation when a new write for the same location is received as the corresponding entry in the primary map is processed.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, and a controller configured to manage a first count, a second count, and a sum value for each of the plurality of memory blocks, the first count being the number of performed random read operations, the second count being the number of performed sequential read operations, the sum value being calculated based on the first count and the second count, and configured to perform a read reclaim operation for a specific memory block among the plurality of memory blocks based on a comparison result of the sum value for the specific block with a reference value.

Abstract: Example implementations relate to data storage. An example includes inspecting a block level input/output (I/O) request to be executed by a block-based storage device, and in response to a determination that the block level I/O request includes a filesystem operation, generating a copy of the block level I/O request. The example also includes parsing the copy of the block level I/O request to extract a plurality of attributes of the filesystem operation, where the parsing is asynchronous to an execution of the block level I/O request by the block-based storage device. The example also includes storing the extracted plurality of attributes of the filesystem operation in an entry of a filesystem operation database, where each entry of the filesystem operation database is associated with a different filesystem operation in a filesystem stored on the block-based storage device.

Abstract: An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.

Abstract: Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Abstract: A system and method for inspecting virtual instances in a cloud computing environment for cybersecurity threats utilizing disk cloning. The method includes: selecting a virtual instance in a cloud computing environment, wherein the virtual instance includes a disk having a disk descriptor with an address in a cloud storage system; generating an instruction to clone the disk of the virtual instance, the instruction when executed causes generation of a cloned disk descriptor, the cloned disk descriptor having a data field including the address of the disk of the virtual instance; inspecting the cloned disk for a cybersecurity threat; and releasing the cloned disk in response to completing the inspection of the cloned disk.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.

Abstract: Embodiments of using command tags are described to prevent data corruption in a multi-path network in an NVMe over Fabrics (NVMe-OF) environment. A command tag is incorporated in a written command send from a host for command identification. Once the host detects an issue of a first link between the host and namespace, the host may immediately send, using a second link, a retry of a command that was previously sent by the host to a first controller via the first link. The retry of the command comprises the same command tag which allows the first and second controllers to detect an execution condition of the first write command, and thus avoiding repeat execution of the first write command by the first controller and the second controller. Therefore, data corruption may be addressed efficiently to the root cause.

Abstract: Managing I/O operations at a storage device, including querying storage device to identify a maximum number of command slots associated with the storage device; providing, to the storage device and at a first throughput, a first set of input/output (I/O) operations for processing at the storage device; updating, based on the first set of I/O operations, a log indicating a number of pending I/O operations to be performed at the storage device; comparing the pending number of I/O operations to the maximum number of command slots of the storage device; determining, based on the comparing, that the pending number of I/O operations is within a first threshold of the maximum number of command slots of the storage device, in response: providing, to the storage device and at a second throughput, a second set of I/O operations for processing at the storage device, the second throughput less than the first throughput.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.

Abstract: Techniques for processing compressed data involve: determining, based on parsing of a header of a compressed data packet, a size of original data corresponding to compressed data, wherein the compressed data packet comprises the header, compressed metadata, and the compressed data. The techniques further involve: allocating, based on the size of the original data, a shared buffer space for receiving and converting the compressed metadata and the compressed data; and storing the compressed data packet in the shared buffer space. The shared buffer space can be used for the receiving and conversion processing of compressed data at the same time, without allocating a separate buffer space for each processing, thereby improving the memory efficiency. Since the allocated shared buffer space is used for both receiving processing and conversion processing, the complexity of configuration of a memory pool is also reduced.