Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.

Abstract: According to an embodiment, a calculator searches for an auxiliary storage device connected to the calculator. If a plurality of auxiliary storage devices are found as a result of the search, the calculator measures a write speed of each of the plurality of auxiliary storage devices. The calculator sets a degree of priority to preferentially utilize a swap space of an auxiliary storage device having a higher write speed. The calculator activates the swap space in accordance with the degree of priority.

Abstract: A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller. The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay.

Abstract: A method and a memory controller for accessing a plurality of memories are provided. The method includes sorting a plurality of blocks of a plurality of memories to correspond to a plurality of disk logical addresses that are sequentially sorted. The plurality of blocks of the plurality of memories include M first blocks of a first memory and N second blocks of a second memory, where M and N are each an integer greater than 1, and the M first blocks of the first memory and the N second blocks of the second memory in the plurality of disk logical addresses are sorted in a non-sequential successive order.

Abstract: A method for performing data access management of a memory device in predetermined communications architecture to enhance sudden power off recovery (SPOR) of page-group-based redundant array of independent disks (RAID) protection with aid of multi-table control using dummy flag and associated apparatus are provided. The method may include: after occurrence of a sudden power off (SPO) event, utilizing the memory controller to perform a SPOR procedure in response to the SPO event, for example, updating a temporary physical-to-logical (P2L) address mapping table corresponding to a first active block to carry the dummy flag in each P2L table entry of at least one P2L table entry corresponding to at least one set of damaged pages; and after performing the SPOR procedure in response to the SPO event, utilizing the memory controller to write subsequent data into at least one set of subsequent pages in the damaged page group.

Abstract: A data processing device according to one embodiment of the present disclosure includes: a memory including at least one unit block composed of a setting information block configured to store setting information required for processing an image signal and a header configured to store basic information about the setting information; and a setting controller configured to receive the setting information from the memory, wherein the setting controller includes: a memory map configured to store the setting information received from the memory; a memory controller configured to sequentially request the basic information and the setting information stored in the at least one unit block; and a setting information signal output unit configured to generate and output a setting information signal and an enable signal corresponding to each unit block using the basic information and the setting information received through the memory controller.

Abstract: One or more techniques and/or computing devices are provided for resilient replication of storage operations. For example, a first storage controller may host first storage having a replication relationship with second storage hosted by a second storage controller. To improve resiliency against transient network issues of a network between the storage controllers, the first storage controller may implement a queue and retry mechanism to retry replication operations not acknowledge back by the second storage controller within a threshold time. The second storage controller may maintain a cumulative sequence number of a latest replication operation performed in order, an operation response map of replication operations performed out of order, and an operation finder map identifying currently implemented replication operations, which may be used to process incoming replication operations. Single write semantics, write order consistency, and reduction of write amplification may be provided.

Abstract: A computer system includes memory hardware configured to store software application files and computer-executable instructions executed by processor hardware. The instructions include determining memory space required for reinstallation of an archived target software application into a directory and preserving the memory space by creating a storage space preservation file in the directory based on the determined memory space. The storage space preservation file is unusable as the archived target software application. The instructions include detecting an execution call to a first replacement executable file and, in response to detecting the execution call, restoring files of the archived target software application to the directory and forwarding the execution call to a first executable file of the archived target software application in the directory.

Abstract: This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

Abstract: A system includes one or more source memory devices of a source computing environment that store a database comprising data files, wherein each of a plurality of data tables of the source computing environment includes data from one or more of the data files, one or more target memory devices of a target computing environment and at least one processor configured to receive a command to copy data files from the source memory devices to the target memory devices, detect that the target memory devices have insufficient memory, calculate a value coefficient for each data table, assign a priority index to each data table based on the value coefficient, order the data files in a copy queue based on the priority index of the data tables, and copy the ordered data files to the target memory devices.

Abstract: Technologies are provided for increasing electronic noise of a memory device during an initialization of the memory device and performing initialization operations, such as memory access centering operations, for the memory device while the electronic noise of the memory device is increased. The electronic noise of the memory device can be increased by increasing a level of ground bounce (or ground noise) during a training phase of the memory device. Increasing the ground noise can comprise increasing an inductance across a memory of the memory device during the training phase. The inductance can be increased by deactivating one or more ground connections of the memory during the memory's training phase. Additionally or alternatively, the inductance can be increased by activating one or more inductors connected to one or more ground connections of the memory during the memory's training phase.

Abstract: The invention discloses a prefetch-adaptive intelligent cache replacement policy for high performance, in the presence of hardware prefetching, a prefetch request and a demand request are distinguished, a prefetch predictor based on an ISVM (Integer Support Vector Machine) is used for carrying out re-reference interval prediction on a cache line of prefetching access loading, and a demand predictor based on an ISVM is utilized to carry out re-reference interval prediction on a cache line of demand access loading. A PC of a current access load instruction and PCs of past load instructions in an access historical record are input, different ISVM predictors are designed for prefetch and demand requests, reuse prediction is performed on a loaded cache line by taking a request type as granularity, the accuracy of cache line reuse prediction in the presence of prefetching is improved, and performance benefits from hardware prefetching and cache replacement is better fused.

Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

Abstract: Securing communications over a compute express link (CXL) is performed by receiving allocation of memory in a memory device and a key identifier (ID) to a trusted execution environment virtual machine (TEE VM); configuring a random key for the key ID by sending a random key configuration request to instruct a device security manager (DSM) of the memory device to configure a memory encryption engine (MEE) of the memory device with the random key and the memory allocation; initializing the allocated memory using the random key; and enabling secure access by the TEE VM to the allocated memory over the CXL by encrypting data transfers from the TEE VM to the memory device using the random key or decrypting data transfers from the memory device to the TEE VM using the random key.

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

Abstract: An operating method of a storage device, the method including; loading journal data from a non-volatile memory device, identifying a cache allocation flag included in the journal data, and restoring meta data corresponding to the journal data to a storage controller in response to the cache allocation flag. Here, the cache allocation flag is a first flag when the meta data are allocated to a meta cache of the storage controller, and the cache allocation flag is a second flag when the meta data are stored to a meta buffer of the storage controller.

Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).

Abstract: A distributed agent for backup and restoration of virtual machines collects backup data and meta-data. The distributed agent includes an agent inside a virtual machine and an agent outside the virtual machine. The two kinds of agents communicate with each other to collect data of different types used to backup and restore virtual machines.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.