Patents by Inventor Ravishankar Sundaresan
Ravishankar Sundaresan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6812142Abstract: A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a “Y”-shaped profile.Type: GrantFiled: November 14, 2000Date of Patent: November 2, 2004Assignee: STMicroelectronics, Inc.Inventors: Loi Nguyen, Ravishankar Sundaresan
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Publication number: 20040178446Abstract: A method is provided for forming a thin film transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A polysilicon gate electrode is formed over a portion of the integrated circuit. Agate oxide layer is formed over the gate electrode. A conformal polysilicon layer is formed over the gate oxide layer and a portion of the integrated circuit. The polysilicon layer is doped with an n-type dopant to form a channel region over the gate electrode. A screen oxide layer is formed over a portion of the polysilicon layer substantially over the gate electrode. The polysilicon layer not covered by the screen oxide layer is doped with a p−-type dopant to form a lightly doped drain region on each side of the channel region. A photoresist layer is formed over a portion of the screen oxide layer and one of the lightly doped drain regions. The polysilicon layer not covered by the photoresist layer is doped with a p+-type dopant. The photoresist layer is then removed.Type: ApplicationFiled: March 29, 2004Publication date: September 16, 2004Inventor: Ravishankar Sundaresan
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Patent number: 6753576Abstract: An asymmetrical polysilicon thin film transistor is formed above a gate electrode on a semiconductor substrate. The transistor is separated from the gate electrode by a gate oxide layer, and includes a channel region immediately above the gate electrode. Highly doped source/drain regions are formed within the polysilicon on either side of the channel region. On the drain side of the channel only, a lightly doped drain region is formed between the channel region and the highly doped drain region. The highly doped source region is immediately adjacent the channel region.Type: GrantFiled: February 9, 1994Date of Patent: June 22, 2004Assignee: STMicroelectronics, Inc.Inventor: Ravishankar Sundaresan
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Patent number: 6566209Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.Type: GrantFiled: August 31, 2001Date of Patent: May 20, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Cher Liang Cha, Ravishankar Sundaresan
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Patent number: 6531750Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.Type: GrantFiled: August 31, 2001Date of Patent: March 11, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Cher Liang Cha, Ravishankar Sundaresan
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Publication number: 20020011629Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.Type: ApplicationFiled: August 31, 2001Publication date: January 31, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Lap Chan, Cher Liang Cha, Ravishankar Sundaresan
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Publication number: 20020003264Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.Type: ApplicationFiled: August 31, 2001Publication date: January 10, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Lap Chan, Cher Liang Cha, Ravishankar Sundaresan
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Patent number: 6297109Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.Type: GrantFiled: August 19, 1999Date of Patent: October 2, 2001Assignees: Chartered Semiconductor Manufacturing Ltd., National University of SingaporeInventors: Lap Chan, Cher Liang Cha, Ravishankar Sundaresan
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Patent number: 6190179Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.Type: GrantFiled: May 9, 1995Date of Patent: February 20, 2001Assignee: STMicroelectronics, Inc.Inventor: Ravishankar Sundaresan
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Patent number: 6107642Abstract: A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening.Type: GrantFiled: July 24, 1997Date of Patent: August 22, 2000Assignee: Chartered Semiconductor Manufacturing CompanyInventor: Ravishankar Sundaresan
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Patent number: 5990528Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.Type: GrantFiled: November 24, 1997Date of Patent: November 23, 1999Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Ravishankar Sundaresan
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Patent number: 5861643Abstract: A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.Type: GrantFiled: September 19, 1997Date of Patent: January 19, 1999Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Tony Wei Chen, Ravishankar Sundaresan
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Patent number: 5723988Abstract: A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.Type: GrantFiled: October 20, 1993Date of Patent: March 3, 1998Assignee: Texas Instruments IncorporatedInventors: Shivaling S. Mahant-Shetti, Mark G. Harward, Lawrence A. Arledge, Jr., Ravishankar Sundaresan
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Patent number: 5721163Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.Type: GrantFiled: June 10, 1996Date of Patent: February 24, 1998Assignee: Chartered Semiconductor Manufacturing Pte, Ltd.Inventor: Ravishankar Sundaresan
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Patent number: 5710461Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.Type: GrantFiled: January 10, 1997Date of Patent: January 20, 1998Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Loi Nguyen, Ravishankar Sundaresan
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Patent number: 5702987Abstract: A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.Type: GrantFiled: August 26, 1996Date of Patent: December 30, 1997Assignee: Chartered Semiconductor Manufacturing Pte LtdInventors: Wei Tony Chen, Ravishankar Sundaresan
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Patent number: 5686334Abstract: A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening.Type: GrantFiled: June 10, 1996Date of Patent: November 11, 1997Assignee: Chartered Semiconductor Manufacturing Pte LtdInventor: Ravishankar Sundaresan
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Patent number: 5554548Abstract: A method is provided for forming a thin film transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A polysilicon gate electrode is formed over a portion of the integrated circuit. Agate oxide layer is formed over the gate electrode. A conformal polysilicon layer is formed over the gate oxide layer and a portion of the integrated circuit. The polysilicon layer is doped with an n-type dopant to form a channel region over the gate electrode. A screen oxide layer is formed over a portion of the polysilicon layer substantially over the gate electrode. The polysilicon layer not covered by the screen oxide layer is doped with a p.sup.- -type dopant to form a lightly doped drain region on each side of the channel region. A photoresist layer is formed over a portion of the screen oxide layer and one of the lightly doped drain regions. The polysilicon layer not covered by the photoresist layer is doped with a p.sup.+ -type dopant.Type: GrantFiled: April 24, 1995Date of Patent: September 10, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventor: Ravishankar Sundaresan
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Patent number: 5395785Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.Type: GrantFiled: December 17, 1993Date of Patent: March 7, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Loi Nguyen, Ravishankar Sundaresan
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Patent number: RE41670Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.Type: GrantFiled: January 20, 2000Date of Patent: September 14, 2010Assignee: STMicroelectronics, Inc.Inventors: Loi Nguyen, Ravishankar Sundaresan