Abstract: The disclosure relates to a support structure for an optical element and an optical element module including such a support structure. The disclosure also relates to a method of supporting an optical element. The disclosure may be used in the context of photolithography processes for fabricating microelectronic devices, such as semiconductor devices, or in the context of fabricating devices, such as masks or reticles, used during such photolithography processes.

Abstract: When the processing circuitry of a signal processor can handle data at a faster rate than the rate of arrival of signal units to be processed, the processor is able to execute a cycle of microcodes for each arriving signal unit. To generate the cycle, the signal processor contains base address reproducing means, for in each cycle reproducing a standard sequence of successive base addresses BA(i) (i=1 . . . N). The base address reproducing means feed microcode selecting means for selecting, in step with each base address and under control of signal data received from the processing circuitry, an associated microcode address MA(i) from a repertory of microcode addresses indicated by the base address BA(i). Selection is implemented by adding each base address BA(i) to an associated index IA(i), determined in dependence on signal data received from the processing circuitry.

Abstract: A MOS integrated logic circuit is described which comprises a plurality of groups (61, 63, 65, 67, 69) of combinatory logic elements. These groups form a cascade in that a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charging means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.

Abstract: A device for multiplying two binary numbers in two's-complement notation having an array for forming bit-wise partial products and a further array for successively forming the result bits therefrom. The modules of the further array form either a full adder or a full subtractor under the control of a one-bit control signal. The negative sign of the most-significant bits of the factors can thus be taken into account. Devices of this kind can be linked in order to realize multiplications with higher precision, variation of the control signal signalling that only the device to which a most significant factor bit is applied takes into account a negative sign. A pipe line product-accumulator device is formed by construction in n-MOS dynamic logic circuits, with an inherent trigger function on the outputs of full adders/subtractors.