Abstract: An encoder of a storage medium encodes data subject to a read operation specified by a storage controller by generating a plurality of symbols representing a soft data stream corresponding to the data subject to the read operation, where each symbol of the plurality of symbols includes (i) a single-bit value number indicating whether the symbol counts 0s or 1s, and (ii) an N-bit count number indicating a bit count associated with the symbol, where N is greater than or equal to two, and the encoder of the storage medium is configured to convey the plurality of generated symbols to the storage controller via electrical interface circuitry connecting the storage medium and the storage controller.

Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.

Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.

Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Abstract: Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.

Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.

Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Abstract: An encoder of a storage medium encodes data subject to a read operation specified by a storage controller by generating a plurality of symbols representing a soft data stream corresponding to the data subject to the read operation, where each symbol of the plurality of symbols includes (i) a single-bit value number indicating whether the symbol counts 0s or 1s, and (ii) an N-bit count number indicating a bit count associated with the symbol, where N is greater than or equal to two, and the encoder of the storage medium is configured to convey the plurality of generated symbols to the storage controller via electrical interface circuitry connecting the storage medium and the storage controller.

Abstract: An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

Abstract: An inversion encoder is configured to receive a plurality of bytes of data for parallel output to a data bus; determine, in parallel, Hamming distances of neighboring pairs of bytes of the received plurality of bytes of data; for each neighboring pair of bytes of the received plurality of bytes, determine, in parallel, for each of the neighboring pairs of bytes, whether a respective Hamming distance satisfies a majority function; if a respective Hamming distance for a particular pair of bytes of the neighboring pairs of bytes satisfies the majority function: set an inversion bit for a second byte of the particular pair of bytes to be the opposite of an inversion bit for a first byte of the particular pair of bytes; invert, or forgo inverting, the second byte based on the inversion bit for the second byte; and provide the second byte for output to the data bus.

Abstract: An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

Abstract: Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.