Patents by Inventor A. Ish,

A. Ish, has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12282111
    Abstract: A method, a system, and a computer program product for localization of wireless devices. At least one of mapping and wireless data describing a physical environment is received. The physical environment includes one or more wireless access points. Using the received mapping and/or wireless data, a location of each of the wireless access points is determined. Using the determined location of the wireless access points, one or more wireless devices positioned in the physical environment are located.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 22, 2025
    Assignee: The Regents of the University of California
    Inventors: Sai Roshan Ayyalasomayajula, Dinesh Bharadia, Shreya Ganesaraman, Ish Jain, Shrivatsan Rajagopalan, Aravind Seetharaman, Sanatan Sharma, Aditya Arun, Chenfeng Wu
  • Publication number: 20250077415
    Abstract: An apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.
    Type: Application
    Filed: July 12, 2024
    Publication date: March 6, 2025
    Inventors: Kishore K. Muchherla, Hong Lu, Mark Ish, Akira Goda
  • Patent number: 12230332
    Abstract: Implementations described herein relate to suspending memory erase operations to perform high priority memory commands. In some implementations, a memory device may detect, while an active stage of an erase operation is being performed by the memory device, a pending memory command with a higher priority than the erase operation. The memory device may selectively suspend the active stage of the erase operation, to allow the pending memory command to be executed, based on the active stage of the erase operation that is being performed and/or a value of a suspend determination timer associated with suspending the active stage of the erase operation.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: February 18, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Shakeel Isamohiuddin Bukhari, Mark Ish
  • Publication number: 20250021391
    Abstract: Systems and methods may use models to generate predictions of specific access rights for users. Further, systems and methods may generate the predictions in an environment in which the availability of the specific access rights change frequently. The access rights, predicted using embodiments described herein, may be both available and associated with user affinities. An interface associated with the primary load management system may be configured to display the predicted access rights for a user operating a user device.
    Type: Application
    Filed: July 29, 2024
    Publication date: January 16, 2025
    Applicant: Live Nation Entertainment, Inc.
    Inventors: Ish Rishabh, Mark Roden, Chris Smith, Spencer Brown, Scott Kline, Krisha Zagura
  • Publication number: 20250023859
    Abstract: In some aspects, the techniques described herein relate to a method including: receiving, at a credential broker, a request including a unique identifier of a client application, wherein the request is from a token software development kit; querying, by the credential broker, an application attestation datastore using the unique identifier of the client application as a lookup key; receiving, at the credential broker and as a result of the querying, a service identifier for a network service; requesting a service ticket from a key distribution center, wherein the service ticket facilitates authentication with the network service; and responding to the token software development kit with a return communication, wherein the return communication includes the service ticket.
    Type: Application
    Filed: August 29, 2023
    Publication date: January 16, 2025
    Inventors: Richard SEIDENSTEIN, Kanishka HETTIARACHCHI, Ish K AHLUWALIA, Darshak KOTHARI, Vimal GANGARAJU, Lakshmiprasanna UMMANENI, Karabi SARMA
  • Publication number: 20250023858
    Abstract: In some aspects, the techniques described herein relate to a method including: sending, by a token software development kit and to a credential broker, a request, wherein the request includes a unique identifier of a client application; receiving, at the token software development kit and from the credential broker; a response, wherein the response includes a service ticket; instantiating a token object in a memory space of the client application, wherein the token object includes the service ticket as a first attribute of the token object; instantiating a context object in the memory space of the client application, wherein the context object includes the token object as an attribute of the context object; providing the context object to the client application; and authenticating, by the client application to a service, using the context object.
    Type: Application
    Filed: August 29, 2023
    Publication date: January 16, 2025
    Inventors: Richard SEIDENSTEIN, Kanishka HETTIARACHCHI, Ish K. AHLUWALIA, Darshak KOTHARI, Vimal GANGARAJU, Lakshmiprasanna UMMANENI, Karabi SARMA
  • Patent number: 12182447
    Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: December 31, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Mark Ish, Yun Li, Scheheresade Virani, John Paul Traver, Ning Zhao
  • Publication number: 20240419523
    Abstract: In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Inventors: Shakeel Isamohiuddin BUKHARI, Mark ISH
  • Publication number: 20240402570
    Abstract: Non-classical light is generated from classical light by providing a non-classical light generation stage with at least one waveguide; inputting classical light into the non-classical light generation stage; and converting at least part of the classical light into non-classical light. The classical light is in a non-fundamental propagation mode of a waveguide of the non-classical light generation stage, and the non-classical light is in a fundamental propagation mode a waveguide of the non-classical light generation stage. The converting does not involve quasi-phase-matching. An input adaptation stage obtains classical light for input into the non-classical light generation stage. In the input adaptation stage, classical light is converted into classical light of a different waveguide propagation mode.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Matteo Santandrea, Marcello Massaro, Ish Dhand
  • Publication number: 20240386193
    Abstract: Certain aspects of the disclosure pertain to inferring a candidate entity associated with a transaction with a machine learning model. An organization identifier and description associated with a transaction can be received as input. In response, an entity embedding, comprising a vector for each entity of an organization based on the organization identifier, can be retrieved from storage. A machine learning model can be invoked with the entity embedding and description. The machine learning model can be trained to infer a transaction embedding from the description and compute a similarity score between the transaction embedding and each vector of the entity embedding. A candidate entity with a similarity score satisfying a threshold can be identified and returned. The candidate entity with the highest similarity score can be identified in certain aspects.
    Type: Application
    Filed: February 6, 2024
    Publication date: November 21, 2024
    Inventors: Natalie Bar Eliyahu, Shirbi Ish-Shalom, Omer Wosner, Dmitry Burshtein
  • Publication number: 20240374410
    Abstract: A formable orthopedic device having at least one first configuration and at least one second configuration, the second configuration being adapted to provide support to at least one limb, the device being made of a thermoplastic polymeric material selected to have an elastic modulus of at least about 1500 MPa when measured according to ASTM D638, a glass transition temperature (Tg) of between about 65° C. and about 120° C., and elongation to break of at least 75% when measured according to ASTM D638, the device being capable to be formed into the second configuration by heating the device to said Tg.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventor: Tamar Ish Cassit
  • Publication number: 20240377991
    Abstract: After receiving a command from a host system to store data, a memory sub-system queues the command to allocate pages of memory cells in a plurality of dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Sanjay Subbarao, Steven S. Williams, Mark Ish, John Edward Maroney
  • Patent number: 12140989
    Abstract: An apparatus includes a first optical circuit and a second optical circuit. The first optical circuit has a network of interconnected interferometers to perform an M-mode universal transformation on N input optical modes that are divided into (M?1) groups of pulses. The first optical circuit also includes M input ports. Each input port of a first (M?1) input ports is configured to receive a corresponding group of pulses in the (M?1) groups of pulses. The first optical circuit also includes M output ports and a first delay line to couple an Mth output port with an Mth input port. The second optical circuit includes a network of beamsplitters and swap gates to perform a (2M?3)-mode residual transformation. The first optical circuit and the second optical circuit are configured to perform an arbitrary N-mode unitary transformation to the N input optical modes via a rectangular architecture.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 12, 2024
    Assignee: Xanadu Quantum Technologies Inc.
    Inventors: Ish Dhand, Shreya Prasanna Kumar, Daiqin Su, Kamil Bradler
  • Publication number: 20240354006
    Abstract: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Ying Huang, Mark Ish
  • Patent number: 12121515
    Abstract: Described herein are novel piperidine urea derived compounds and their pharmaceutical compositions for the treatment of conditions and diseases mediated by soluble epoxide hydrolase.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: October 22, 2024
    Assignee: NeuroPn Therapeutics, Inc.
    Inventors: Ish Khanna, Sivaram Pillarisetti
  • Patent number: 12111774
    Abstract: A computing system uses AES-XTS encryption to encrypt data of a first part of first data stream using a tweak key, a data key, an initial tweak value, in a first encryption session, store the encrypted first part, then encrypts a second part of the first data stream in a second encryption session commenced after the termination of the first encryption session; and store the encrypted second part in the encrypted data store. The second part of the first data stream is encrypted using a modified tweak value computed based on the initial tweak value, the tweak key, and a block index of a last cipher block of the first part of the first data stream.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: October 8, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeny Yankilevich, Vadim Makhervaks, Robert Groza, Jr., Yi Yuan, Oren Ish-Am
  • Publication number: 20240294516
    Abstract: Described herein are novel piperidine urea derived compounds and their pharmaceutical compositions for the treatment of conditions and diseases mediated by soluble epoxide hydrolase.
    Type: Application
    Filed: April 23, 2024
    Publication date: September 5, 2024
    Applicant: NeuroPn Therapeutics, Inc.
    Inventors: Ish Khanna, Sivaram Pillarisetti
  • Patent number: 12079065
    Abstract: In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: September 3, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shakeel Isamohiuddin Bukhari, Mark Ish
  • Publication number: 20240291624
    Abstract: Some embodiments of the invention provide a method for mitigating inter-region interference for multiple regions serviced by multiple RAN (Radio Access Network) base stations. The method is performed for each region serviced by each particular RAN base station. The method identifies a set of one or more sub-regions receiving interfering signals from other RAN base stations.
    Type: Application
    Filed: July 12, 2023
    Publication date: August 29, 2024
    Inventors: Yang Yang, Neha Paranjape, Deepa Muthunoori, Ish Kumar Jain
  • Publication number: 20240292390
    Abstract: Some embodiments of the invention provide a method for operating a first base station of a radio access network (RAN). At the first base station, the method receives a set of allow and block policies for allocating carrier resources to carrier beams utilized by the first base station for mobile devices within a first region serviced by the first base station, said first region located near a second region serviced by a second base station. At the first base station, the method identifies a first mobile device operating in the first region. At the first base station, the method uses the set of allow and block policies to allocate carrier resources to a carrier beam used to communicate with the first mobile device in the first region.
    Type: Application
    Filed: July 12, 2023
    Publication date: August 29, 2024
    Inventors: Yang Yang, Neha Paranjape, Deepa Muthunoori, Ish Kumar Jain