Abstract: A voltage detector including a voltage following circuit connected to a power supply and operable to follow a voltage value of the power supply, a selectable threshold point circuit connected to the voltage following circuit and operable to select one of a plurality of values for a threshold point of the power supply, and a switch circuit coupled to the selectable threshold point circuit and the voltage following circuit, the switch circuit cooperating with the selectable threshold point circuit to generate an output indicating whether the value of the power supply has increased above or decreased below the selected value for the threshold point in response to the followed value of the power supply.

Abstract: A non-volatile latch circuit that has minimal control circuitry is disclosed. The non-volatile latch circuit is typically used in applications where only several bits of data need to be stored in non-volatile memory. The non-volatile latch circuit can be programmed and read using three control signals: a programming voltage/supply voltage signal, a data in signal, and a read/{overscore (write)} signal. By using fewer control signals, the number of transistors used to implement the control circuitry within the non-volatile latch circuit is reduced and thus the non-volatile latch circuit consumes less chip area/volume on an integrated circuit device.

Abstract: In accordance with the present invention a mode select circuit includes a bias circuit and a voltage level encoder. The mode select circuit further includes a mode select terminal capable of being selectively coupled to one or more of a plurality of configuration elements to bias the mode select terminal to one of a plurality of predesignated voltages. The bias circuit is coupled to the mode select terminal for biasing the terminal to one of the predesignated voltages when the mode select terminal is not coupled to any of the configuration elements. The voltage level encoder is coupled to the mode select terminal for providing one of a plurality of voltage level codes on a plurality of voltage level encoder output terminals in response to the mode select terminal being biased to a corresponding one of the plurality of predesignated voltages.

Abstract: A method and circuits for generating a start-up signal to force a bistable reference circuit into a conducting state. The start-up signal ensures that the reference circuit operates to provide a desired output signal when power is applied. The start-up signal is self-generated and self-canceled, rather than relying on an externally supplied pulse, and is input to the reference circuit via a hysteresis circuit (e.g., Schmitt inverter).

Abstract: A voltage regulator for coupling to an unregulated power source and regulating a voltage and conveying a current received from such source includes a bias voltage generator and a voltage translator which together dissipate virtually zero power while providing such voltage regulation and current conveyance. The bias voltage generator produces a stable reference current for purposes of generating stable bias voltages for the voltage translator. The voltage translator generates a regulated output voltage by translating a reference voltage potential (e.g., circuit ground) upwards by an amount equal to multiple depletion mode transistor threshold voltages.

Abstract: A bandgap voltage reference circuit includes a feedback controlled current mirror, a bandgap voltage generator, and a voltage comparator. The current mirror, in response to a feedback control signal from the voltage comparator, generates a controllable reference current. The bandgap voltage generator generates two reference voltages based upon conduction of the reference current from the current mirror through two PN diodes having different emitter areas. The voltage comparator compares the two reference voltages and generates the feedback control signal for the current mirror. Such a bandgap voltage reference circuit simultaneously generates a bandgap voltage reference and a current mirror reference while also being operable over a wide power supply voltage range and down to very low power supply voltage values.

Abstract: A voltage comparator produces a current output as a function of the differential input voltage. Three transfer functions are detailed. In the linear transfer mode the output varies linearly in the transition region and swings between zero and a well-defined current value. In a truncated response mode, the output is zero for zero differential input voltage, remains at zero for one input voltage polarity, and rises for the other polarity input linearly to a well-defined current value. In the folded response mode the output current is zero for zero differential input and rises linearly in the transition region to a well-defined current value for either polarity of differential input. While a CMOS form of construction is preferred, bipolar construction is also shown.

Abstract: A four phase clock generator, which can be employed to operate a charge pump, is configured using coupling elements that ensure that the four phases are non-overlapping. Each of the circuits used to generate one of the four phases of the clock signal consists of a logic block, a buffer block whose delay can be controlled, and a cascade of inverters for amplifying the signal produced by the circuit. The buffer block acts both to invert the signal produced by the logic block, and to delay the signal output by the logic block by an amount which can be varied based on control signals which mirror a current source. The amount of signal delay produced by the buffer is used to adjust the relative timing of the rising and falling edges of each of the four phases of the clock signal (and hence the frequency of the signal) in response to the demand placed upon a charge pump which is driven by the clock signal generator.

Abstract: A bandgap constant voltage circuit employs a resistor network to pass the currents conducted by a pair of PN junction transistors. These two transistors are operated at differential current densities. A resistor is connected in series with the lower current density transistor. A comparator has its input terminals coupled to the circuit nodes representing the higher current density transistor and the combined lower current density transistor and series-connected resistor. The comparator output is a current that is coupled to the resistor network which is proportioned with respect to the series-connected resistor to produce a voltage that, when combined with the voltage drop across the high current density transistor, is equal to the semiconductor bandgap. A negative feedback loop, employing re-entrant connected current mirrors, is employed to adjust all of the circuit currents and is incorporated into the comparator so that the voltage applied to the resistor network is maintained at the bandgap value.

Abstract: In order to permit the selection of aspect ratio for a given memory size, a semiconductor array utilizes switches to segment bit line columns, where each segment is associated with a specific set of memory locations and their respective data latches. After all of the data latches are loaded, the switches segment the bit line columns to allow simultaneous programming of those memory locations cells associated with each set of data latches. This sequence is repeated until all desired data storage cells are programmed.

Abstract: A four phase clock generator, which can be employed to operate a charge pump, is configured using coupling elements that ensure that the four phases are non-overlapping. Two of the phases are created with delay buffers that have substantial delays that mainly determine the clock frequency. The delay buffers and coupling elements produce delays that are made variable in response to a control current. This provides a clock whose frequency is proportional to a control current.

Abstract: A charge pump for increasing the amplitude of a voltage supply signal is disclosed. The charge pump includes an auxiliary pump, a buffer stage, and a main pump. The auxiliary pump generates several intermediate voltage signals in response to a pair of complementary clock signals. Each intermediate voltage signal has a different amplitude which is greater than the amplitude of the voltage supply signal. The buffer stage increases the amplitudes of the pair of complementary clock signals in response to the several intermediate voltage signals generated by the auxiliary pump. The main pump increases the amplitude of the voltage supply signal in response to the pair of increased amplitude complementary clock signals generated by the buffer stage.

Abstract: An integrator circuit is connected to a capacitor that is to be measured and the capacitor driven by a read pulse. A first switch grounds the integrator input between read pulses and a second switch applies a bias input to the integrator. The bias is selected so that the integrator is active and its output high. Then, during the read pulse interval, the integrator will hold its input close to ground so that the capacitor to be measured will transfer a maximum charge to the integrator feedback capacitor. Additionally, the stray capacitance at the integrator input has little effect and the output will be a strong function of the value of the capacitor to be measured. The circuit has application in capacitor measurement and is useful as a ferroelectric memory preamplifier which acts to amplify the difference in capacitance produced by the polarization state of a ferroelectric memory capacitor. A CMOS preferred embodiment is disclosed in the form of a memory sense preamplifier.

Abstract: A CMOS current sense amplifier is composed of an output inverter gate, a combined driver and biasing stage that biases the output inverter gate and drives its transistors, and an input stage that acts to reduce the input voltage swing. The circuit responds rapidly to input current changes and is therefore useful in sensing the currents in large memory arrays that have large shunt capacitance values.

Abstract: A self-timed transition detector is provided that responds to a change in the logic level of a signal by generating a change-indicator flag. The change-indicator flag is held active until an event initiated by the change-indicator flag has been completed. Completion of the event cancels the change-indicator flag, thereby verifying the completion of the event.

Abstract: A CMOS buffer is disclosed having a reference potential that provide TTL logic response. The circuit is configured to draw substantially zero current. A reference potential generator develops a potential that is one N channel transistor threshold above about 1.2 volts for TTL compatibility. A single reference potential generator will provide a potential for a plurality of buffers so that its dissipation is low and is shared among the buffers. The result is a low power buffer circuit that is compensated for variations in supply voltage, temperature and device parameters.

Abstract: A compensation arrangement is shown for the diffused column line resistance in an N channel metal gate read only memory. The circuit employs a dummy column which has a transistor at each possible location operated from the same decoder that operates the metal gate rows. A current sense circuit clamps the column pull-up end of the dummy column line and provides a correction signal that is fed to the pull-up devices in the memory columns. A second current sense circuit clamps the dummy column sense amplifier end of the column line and provides a correction signal that can be used to compensate the reference currents in column sense amplifiers using differential current sensing.

Abstract: A differential current sense amplifier is shown suitable for high speed semiconductor memory sensing. A reference current generation circuit is also developed for operating a plurality of sense amplifiers.

Abstract: A current responsive sense amplifier circuit is used in a semiconductor memory. The circuit includes means for reducing the voltage swings that are associated with the binary logic states.

Abstract: A two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor. D-C gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased one threshold below V.sub.DD and the N-channel transistor is biased one threshold above ground. The biasing voltages are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. This form of biasing renders the circuit class B regardless of the source to drain voltage and ensures low current operation. A crystal oscillator created using such an inverter and biasing will operate at voltages substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator.