Abstract: A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.

Abstract: The present disclosure relates, according to some embodiments, to a multilayered polyimide film comprising a peelable base layer, and a polyimide layer adhered in contact with the peelable base layer. A peelable base layer may be derived from a reaction comprising a diamine compound and a dianhydride compound, wherein the peelable base comprises a polyimide and a structure according to formula (I): wherein n is a number of repeating units. According to some embodiments, a quantity of silicon atoms present in a peelable base layer comprises about 1% to about 12% of a total weight of the peelable base layer.

Abstract: A network as a service (NaaS) service cross-domain orchestration method to implement an end-to-end NaaS service in a multi-domain network that includes multiple network domains where the method includes obtaining information about a first user-to-network interface (UNI) and information about a second UNI in a multi-domain network according to a received NaaS service request, where the NaaS service request is used to request to establish an NaaS service between a first terminal and a second terminal; querying domain resource information to obtain a cross-domain path between the first UNI and the second UNI; determining network domains that the cross-domain path passes through, and obtaining a first connection requirement and a second connection requirement of each network domain of the network domains that the cross-domain path passes through; and sending the first connection requirement and the second connection requirement to a control device in each network domain.

Abstract: An approach is provided for managing processing rules used to process electronic data in computer networks. An application provides the capability for users to define and manage classifications for electronic data. The application also provides the capability for users to define and manage processing rules for each classification. This may include specifying, for each processing rule, a classification to which the processing rule corresponds, one or more conditions under which the processing rule is to be applied and optionally, not applied, a priority for the processing rule, and one or more actions to be performed. The priority may be used to determine which rule is to be applied when more than one rule corresponds to a classification. The application supports the definition and management of classifications and rules on a logical group-by-logical group basis.

Abstract: A structural connector for assembling a plurality of structural members includes a main shank, a first bolt extending though the main shank, a first plug threadedly engaging a first blot shaft of the first bolt, a second bolt extending through the main shank and the first bolt shaft, and a second plug threadedly engaging a second bolt shaft of the second bolt. Each of two shank ends of the main shank, a first bolt head of the first bolt, a first plug head of the first plug, a second bolt head of the second bolt, and a second plug head of the second plug is configured to threadedly engage a structural connecting end of each of the structural members.

Abstract: A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug adjacent to the first gate structure and contact the first spacer, and a first overhang feature disposed on an upper end of the first spacer.

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.

Abstract: In one embodiment, a method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit is provided. The method comprises providing a silicon on insulator (SOI) wafer and fabricating an isolated first silicon region and an isolated second silicon region on the SOI wafer wherein each of the first silicon region and the second silicon region is bounded on its sides by a trench filled with insulator material. The method further comprises fabricating an active area comprising GaN on each of the first silicon region and the second silicon region to form the first transistor circuit and the second transistor circuit and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

Abstract: A combined shower with a gravity switch mechanism includes a wall-fixed shower, a handheld shower and a water diversion component, the water diversion component includes a water inlet, two water outlets respectively connected to the wall-fixed shower and handheld shower, and a switching component which is used to switch the waterway communication between the water inlet and two water outlets. The shower also includes a gravity switch mechanism and an attachment portion. The attachment portion interacts with the switching component to drive the activation of the switching component to trigger the switch to make the handheld shower activate or remain static relative to the position of the wall-fixed shower.

Abstract: An SEM image is acquired. The SEM image shows a metal line and a via hole disposed above the metal line. The via hole exposes a portion of the metal line vertically aligned with the via hole. A first portion and a second portion of the via hole are each vertically not aligned with the metal line and are disposed on opposite sides of the metal line. The acquired SEM image is processed to enhance a contrast between the first and second portions and their surrounding areas. A first dimension of the first portion and a second dimension of the second portion of the via hole are measured in a first direction. The first direction is different from a second direction along which the metal line extends. An overlay between the via hole and the metal line is determined based on the first dimension and the second dimension.

Abstract: A method of providing an oxidation resistant coating is disclosed. The method includes providing a substrate having a first surface and cooling holes. A portable coating device includes electro-spark deposition (ESD) equipment and an ESD torch connected with the ESD equipment. The ESD torch has an inert gas source and a rotary electrode conductive material. The rotary electrode is positioned within the ESD torch, and is shielded by an inert gas. The rotary electrode applies a compositionally controlled protective coating to the first surface of the substrate. Then the rotary electrode is inserted into the cooling hole and generates an electrospark between rotary ESD electrode and the substrate to form a rounded edge and deposit a coating of electrode material alloy at a cooling hole edge.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: The present invention is related to a radiolabeled active targeting pharmaceutical composition, including: a bioconjugate and a radionuclide, wherein the bioconjugate includes a biomolecule and a metal nanoparticle, wherein the biomolecule has an affinity for receptors on the surface of a cell membrane and is selected from the group consisting of a peptide and a protein. The present invention further provides a method for evaluating a thermal adjuvant therapy for tumors and a kit thereof. The above-mentioned pharmaceutical composition is applied to evaluate a tumor accumulation time, so as to establish the optimal policy for a radiofrequency- or laser-induced thermal adjuvant therapy for tumors.

Abstract: A system for background image subtraction includes a computing device coupled with a 3D video camera, a processor o£ the device programmed to receive a video feed from the camera containing images of one or more subject that include depth information. The processor, for an image: segments pixels and corresponding depth information into three different regions including foreground (FG), background (BG), and unclear (UC); categorizes UC pixels as FG or BG using a function that considers the color and background history (BGH) information associated with the UC pixels and the color and BGH information associated with pixels near the UC pixels; examines the pixels marked as FG and applies temporal and spatial filters to smooth boundaries of the FG regions; constructs a new image by overlaying the FG regions on top of a new background; displays a video feed of the new image in a display device; and continually maintains the BGH.

Abstract: A fin field effect transistor (FinFET) on a silicon-on-insulator and method of forming the same are provided in the present invention. The FinFET includes first fin structure, second fin structure and an insulating layer. The first fin structure and the second fin structure are disposed on a substrate. The insulating layer covers the first fin structure and the second fin structure and exposes a first portion of the first fin structure and a second portion of the second fin structure. The first fin structure has a first height and the second fin structure has a second height different from the first height, and a top surface of the first fin structure and a top surface of the second fin structure are at different levels.

Abstract: Using a high sample rate dPES, together with pulsed heater and lock-in technique, to improve dPES SNR for contact detection between the head and media surface. Steps of powering a transducing head actuator with pulsed input signal at a select data track offset from a previously-written to data track of the storage medium, where the pulsed input signal has select amplitude and duty cycle to simulate a response signal, and further locking in an amplitude with respect to the heater frequency, can lead to a determination of level of heater power for initiating contact between the transducing head and the storage medium.