Abstract: A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain.

Abstract: A clamping structure includes an object, a clamping component and an elastic component. The object has a hole and a containing space, wherein the containing space is connected to the hole. The clamping component includes a pillar, a bump and a head portion, wherein the bump and the head portion are connected to the pillar, and the pillar is adapted to be inserted into the hole and rotated such that the bump moves to the containing space. When the bump is located in the containing space, the elastic component is compressed between the object and the head portion, and the bump is positioned at the containing space by elastic force of the elastic component, such that the clamping component is fastened to the object.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. The protection element has an upper portion and a lower portion between the upper portion and the gate stack, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

Abstract: A development device includes a developer container, a developer bearing member, a mixing/transporting member, an opening/closing member, and a drive mechanism. The developer container contains a developer. The developer bearing member is rotatably supported by the developer container. The developer bearing member also has a surface facing an image bearing member on which an electrostatic latent image is to be formed. The developer is borne on the surface of the developer bearing member. The mixing/transporting member mixes and transports the developer in the developer container. The opening/closing member opens and closes a developer outlet for discharging an excess of the developer in the developer container. The drive mechanism drives the opening/closing member in association with driving of the developer bearing member or the mixing/transporting member to open the developer outlet.

Abstract: A semiconductor process includes the following steps. A fin on a substrate is provided. Spacers are formed only on sidewalls of the fin, where a top surface of the fin is higher than or equal to top surfaces of the spacers. An epitaxial structure is formed on the fin. The present invention also provides a fin-shaped field effect transistor including a fin, spacers and an epitaxial structure. The fin is located on a substrate. The spacers are disposed only on sidewalls of the fin, where a top surface of the fin is higher than or equal to top surfaces of the spacers. The epitaxial structure is disposed on the fin.

Abstract: A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed.

Abstract: Broadband antenna for wireless communication device is disclosed. The broadband antenna includes a grounding portion, a feeding portion, a connecting portion, a first radiation body connected to an end of the connecting portion, and second radiation body connected to another end of the connecting portion opposite to the first radiating body. The first radiating body and the second radiating body are symmetrical to each other with respect to the connecting body. The feeding portion is connected to an end of the first radiating body away from the second radiating body, the grounding portion is connected to an end of the second radiating body away from the first radiating body.

Abstract: The disclosure provides an organic light-emitting device. The organic light-emitting device includes a substrate, and an organic light-emitting pixel array disposed on the substrate. The organic light-emitting pixel array includes a plurality of pixels. Each pixel includes a first sub-pixel and a second sub-pixel. Each sub-pixel includes a first electrode, an organic light-emitting element, a second electrode, and an optical path adjustment layer. The optical path adjustment layer is disposed between the first electrode and the second electrode. Particularly, the thickness of the optical path adjustment layer of the first sub-pixel is substantially equal to the thickness of the optical path adjustment layer of the second sub-pixel.

Abstract: A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Abstract: The present disclosure relates to an RRAM (resistive random access memory) cell having a top electrode with a geometry configured to improve the electric performance of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a lower insulating layer with a micro-trench located over a lower metal interconnect layer disposed within a lower inter-level dielectric (ILD) layer that overlies a semiconductor substrate. A bottom electrode is disposed over the micro-trench, and a dielectric data storage layer is located over the bottom electrode. A top electrode is disposed over the dielectric data storage layer. The top electrode has a protrusion that extends outward from a bottom surface of the top electrode at a position overlying the micro-trench. The protrusion generates a region having an enhanced electric field within the dielectric data storage layer, which improves performance of the RRAM cell.

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.

Abstract: A notebook component within a note-taking application is utilized as a centralized mechanism for recording notations and providing documentation related to a particular meeting. The meeting participants are provided with centralized access to the notebook component and thus are able to update the notebook record of the meeting collaboratively and in real time. In addition to user-driven updates, updates may also be generated on an automatic or semi-automatic basis. Updates may be made before, during or after the actual meeting. Updates may originate from an application data source outside of the note-taking application itself.

Abstract: A reflector configured for guiding light emitted from a light emitting diode (LED) light source includes four reflective walls. The reflective walls are connected side-by-side to cooperatively define a cavity. The cavity has a first opening and a second opening at opposite ends thereof. An inner diameter of the cavity gradually decrease as it extends from the second opening toward the first opening. The LED light source is located at the second opening of the cavity. Light emitted from the LED light source enters into the cavity and is reflected by the at least one reflective wall toward the first opening of the cavity. An illuminating device and a backlight module using the reflector are also provided.

Abstract: The present invention provides a pharmaceutical composition for the treatment and prophylaxis of angina and myocardial infarction, wherein a combination of a tea extract (catechins) and an antianginal drug are proved therapeutically potent in treating angina and mycocardial infarction induced from myocardial ischemia. The present invention also provides a use of a tea extract (catechins) in treating and preventing angina.

Abstract: A method for displaying SIM card slot information for use in a device including M SIM card slots, each of which may have a SIM card inserted therein or no SIM card inserted therein. The method includes the following steps. A set of predetermined rules are first determined by the device. Statuses of the M SIM card slots corresponding to the set of predetermined rules are then acquired. Information regarding N of the M SIM card slots are displayed on a display unit of the device according to the set of predetermined rules determined by the current associated network and the acquired statuses of the M SIM card slots, where N<M and N>=1.

Abstract: In a method of implementing a positioning system a buffer is configured to store a buffer record for each of a plurality of position fixes determined by the receiver and a database is configured to store a database record for each of the position fixes. Buffer records are accumulated, with each buffer record corresponding to one of the position fixes determined by the receiver. A first threshold position near an area in which a degradation event occurs is identified and recorded in a first database record. A second threshold position near the area is identified in a second database record. The second threshold position is indicated by one of the position fixes outside of the area and is proximate to a position at which the degradation event ends.

Abstract: A an optical module integrated package includes a substrate, a light-receiving chip mounted in a light-receiving region of the substrate, an electronic component mounted in the substrate, a cover mounted on the substrate and having a light-receiving chip disposed above the light-receiving hole, and a lens fixedly mounted in the light-receiving hole of the cover. Thus, the optical module integrated package not only have the chip and the electronic component integrated therein to reduce the packaging cost and to improve the yield but also provide a light filtering, focusing or diffusing effect to enhance optical recognition accuracy.